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ISSCC 2026
Session 9
Wireless
A Multi-Coil Scalable Energy-Shared Wireless Power Receiver Network for Distributed Time-Division-Multiplexing Somatosensory Cortex Stimulation
Abstract This work presents a system-level scalable wireless power receiver (RX) network for miniaturized distributed somatosensory cortex stimulation. By interconnecting the power outputs of all RX cells in the network,
ISSCC 2026
Session 9
Wireless
An Output-Domain-Independent Single-Transmitter-Dual-Receiver Wireless Power Transfer System with Detuned-Tank and Time-Multiplexing Control for Adaptive Power Distribution
Abstract This paper presents an output-domain-independent single-transmitter-dual-receiver wireless power transfer system. The proposed detuned-tank and time-multiplexing control enable adaptive power distribution, preve
ISSCC 2026
Session 9
Wireless
A 91%-Efficiency Single-Stage Bipolar Quad-Output Regulating Rectifier with Event-Driven Output Power Enhancement via Coil-Reused DC-DC for Wireless Power Transfer
Abstract A bipolar quad-output regulating rectifier for wireless power transfer (WPT) is presented. Using only five power switches, it provides four independently regulated bipolar outputs. A coil-reused DC-DC mode susta
ISSCC 2026
Session 9
Wireless
A Single-Power-Link 13.56MHz Wireless Power and Data Transfer System with Synchronized Phase-Shifted Time-Multiplexing Dual Uplinks for Implantable Voltammetry
Abstract A 13.56MHz wireless power and data transfer (WPDT) system for implantable voltammetry sensor is presented. With the synchronized phase-shifted time-multiplexing technique, the system uses a single power link to
ISSCC 2026
Session 8
Wireline I/O
A 72Gb/s/pin Single-Ended Simultaneous Bi-Directional Transceiver with C-Peaking Leakage Cancellation and Dual-Loop Hybrid Impedance Calibration for Chiplet Interfaces
Abstract This paper presents a 72Gb/s/pin single-ended simultaneously bi-directional (SBD) TRX in 28nm CMOS. Capacitive peaking leakage cancellation (CPLC) suppresses the high-frequency leakage due to the main and hybrid
ISSCC 2026
Session 8
Wireline I/O
A 0.292pJ/b 56Gb/s/wire Capacitively Driven Simultaneous Bidirectional Transceiver with PVT/Mismatch Tracking for XSR and D2D Interfaces in 28nm CMOS
Abstract A low-power (0.292pJ/b), high-bandwidth (56Gb/s/wire) single-ended capacitively driven simultaneous bi-directional (CD-SBD) TRX with PVT tolerance is proposed. Capacitive driving reduces power and self-interfere