ISSCC 2008

2008

228 篇论文 · RF & Wireless (25) · Wireline I/O (25) · Data Converters (24) · Memory (21)

ISSCC 2008 Session 16 Digital Circuits
iVisual: An Intelligent Visual Sensor SoC with 2790fps CMOS Image Sensor and 205GOPS/W Vision Processor
Chih-Chi Cheng1, Chia-Hua Lin1, Chung-Te Li1, Samuel Chang1,
in surveillance, healthcare, intelligent vehicle control, human-machine interfaces, etc. Hardware solutions exist for video analysis. Analog on-sensor processing solutions [1] feature image sensor integration. However, t
Chia-Jung Hsu2, Liang-Gee Chen1 1 National Taiwan University, Taipei,
ISSCC 2008 Session 16 Digital Circuits
A 125GOPS 583mW Network-on-Chip Based Parallel Processor with Bio-inspired VisualAttention Engine
Kwanho Kim, Seungjin Lee, Joo-Young Kim, Minsu Kim,
reduce the complexity of object recognition by decreasing the amount of image data to be processed. As Fig. 16.2.1 illustrates, salient parts of a scene are roughly selected by the visual attention mechanism in advance s
Donghyun Kim, Jeong-Ho Woo, Hoi-Jun Yoo KAIST, Daejeon, Korea The visu
ISSCC 2008 Session 16 Digital Circuits
A 360mW 105Mb/s DVB-S2 Compliant Codec based on 64800b LDPC and BCH Codes enabling SatelliteTransmission Portable Devices
P. Urard1, L. Paumier2, V. Heinrich1, N. Raina3, N. Chawla3, 1
Services compliant 2nd Generation Satellite Digital Video Broadcast (DVB-S2) [1] codec is presented. Previously published silicon implementations respecting this stringent standard reports power consumption between 800mW
STMicroelectronics, Crolles, France, 2STMicroelectronics, Grenoble, Fr
ISSCC 2008 Session 16 Digital Circuits
A 512GOPS Fully-Programmable Digital Image Processor with full HD 1080p Processing Capabilities
Sumito Arakawa, Yuji Yamaguchi, Satoshi Akui, Yasushi Fukuda,
Hirofumi Sumi, Hiroshi Hayashi, Masahiro Igarashi, Kei Ito, Hidetoshi Nagano, Masatoshi Imai, Naosuke Asari Sony, Tokyo, Japan The introduction of high-resolution CMOS image sensors [1] has encouraged the development of
ISSCC 2008 Session 16 Digital Circuits
A 242mW 10mm2 1080p H.264/AVC High-Profile Encoder Chip
Yu-Kun Lin, De-Wei Li, Chia-Chun Lin, Tzu-Yun Kuo, Sian-Jin Wu,
has been adopted as the major coding standard in recently popular high definition video due to its excellent coding efficiency. Several implementations have been developed [1-3], but, their performance is limited to base
Wei-Cheng Tai, Wei-Cheng Chang, Tian-Sheuan Chang National Chiao-Tung
ISSCC 2008 Session 16 Digital Circuits
A 320mV 56µW 411GOPS/Watt Ultra-Low Voltage Motion Estimation Accelerator in 65nm CMOS
Himanshu Kaul, Mark Anders, Sanu Mathew, Steven Hsu,
the most performance and power-critical operation in video encoding applications, where a wide range of throughput and power constraints are required to handle a variety of video resolution, frame rate and application sp
Amit Agarwal, Ram Krishnamurthy, Shekhar Borkar Intel, Hillsboro, OR M
ISSCC 2008 Session 16 Digital Circuits
A 65nm Sub-Vt Microcontroller with Integrated SRAM and Switched-Capacitor DC-DC Converter 256 to improve speed and read reliability; devices in the readbuffer are lengthened to achieve higher speed and lower read current variability in sub-Vt.
Joyce Kwong1, Yogesh Ramadass1, Naveen Verma1, Markus Koesler2,
Korbinian Huber2, Hans Moormann2, Anantha Chandrakasan1 A custom timing closure approach was developed to account for increased delay variability in sub-Vt. As shown in Fig. 16.7.3, delay distributions of timing paths in
ISSCC 2008 Session 17 Other
A Discrete-Time Mixing Receiver Architecture with Wideband Harmonic Rejection
Z. Ru, E.A.M. Klumperink, B. Nauta
Recently several CMOS software-defined radio (SDR) demonstrators have been presented using mixers as the wideband downconverter [1,2]. Meanwhile, the feasibility of RF samplers as downconverter has also been demonstrated
University of Twente, Enschede, Netherlands
ISSCC 2008 Session 17 Other
A Single-Inductor Dual-Band VCO in a 0.06mm2 5.6GHz Multi-Band Front-End in 90nm Digital CMOS
J. Borremans1,2, S. Bronckers1,2, P. Wambacq1,2, M. Kuijk2, J. Craninckx1, 1
applications. Expensive scaled CMOS processes are readily used as a technology enabler to provide adequate performance. The high implementation cost of circuits in such processes is justified by the added functionality o
IMEC, Leuven, Belgium, 2Vrije Universiteit Brussel, Brussels, Belgium
ISSCC 2008 Session 17 Other
A Wideband Balun LNA I/Q-Mixer combination in 65nm CMOS
Stephan Blaakmeer1, Eric Klumperink1, Domine Leenaerts2, Bram Nauta1, 1
University of Twente, Enschede, Netherlands NXP Semiconductors, Eindhoven, Netherlands Wideband receivers are required for many applications including the upcoming software-defined radio (SDR) architectures and ultra-wid
ISSCC 2008 Session 18 Other
Measurement of Nano-Displacement Based on In-Plane Suspended-Gate MOSFET Detection Compatible with a Front-End CMOS Process
E. Colinet1, C. Durand23, P. Audebert1, P. Renaux1, D. Mercier1,
L. Duraffourg1, E. Ollier1, F. Casset1, P. Ancey2, L. Buchaillot3, A. M. Ionescu4 1 CEA-LETI, Grenoble, France, 2STMicroelectronics, Crolles, France IEMN, Villeneuve d’Ascq, France, 4EPFL, Lausanne, Switzerland 3 Nano-el
ISSCC 2008 Session 18 Other
Ultra-Thin Chips on Foil for Flexible Electronics
Horst Rempp, Joachim Burghartz, Christine Harendt, Nicoleta Pricopi,
thin-film-transistors on foil and ultra-thin chips on foil are technologies currently pursued to support the strongly emerging market for flexible electronics. Ultra-thin CMOS chips [1] on foil will not only provide solu
Marcus Pritschow, Christian Reuter, Harald Richter, Inge Schindler, Ma
ISSCC 2008 Session 18 Other
A 0.18µm CMOS Integrated Sensor for the Rapid Identification of Bacteria
N. Nikkhoo, C. Man, K. Maxwell, P. G. Gulak
There is widespread demand for a low-cost, rapid, selective and sensitive method for detecting bacteria in medical diagnosis, and food-safety inspection. Traditional methods, such as polymerase chain reaction and cell cu
University of Toronto, Toronto, Canada
ISSCC 2008 Session 19 Clocking & PLLs
Spurious -Tone Suppression Techniques Applied to a Wide-Bandwidth 2.4GHz Fractional-N PLL
Kevin J. Wang1, Ashok Swaminathan2, Ian Galton1, 1
University of California at San Diego, La Jolla CA NextWave Broadband, San Diego, CA A major problem with fractional-N PLLs is that their phase noise contains fractional spurs, i.e., spurious tones at multiples of fref t
ISSCC 2008 Session 19 Clocking & PLLs
A 3GHz Fractional-N All-Digital PLL with Precise Time-to-Digital Converter Calibration and Mismatch Correction
Colin Weltin-Wu1,2, Enrico Temporiti3, Daniele Baldi3, Francesco Svelto2, 1
area of intense investigation, motivated by low supply headroom and poor analog performance in ultra-scaled CMOS. RF frequency synthesis is particularly amenable to a digital architecture and has already seen integration
Columbia University, 2Università degli Studi di Pavia, Pavia, Italy ST
ISSCC 2008 Session 19 Clocking & PLLs
A 1GHz Fractional-N PLL Clock Generator with Low-OSR ΔΣ Modulation and FIR-Embedded Noise Filtering
Xueyi Yu, Yuanfeng Sun, Li Zhang, Woogeun Rhee, Zhihua Wang
Offering less than 1ppm frequency resolution, a ΔΣ fractional-N PLL enables flexible frequency planning and reliable spread spectrum modulation for digital clock generation [1, 2]. Use of low-cost ring VCOs however, mand
Tsinghua University, Beijing, China
ISSCC 2008 Session 19 Clocking & PLLs
A 90µW 12MHz Relaxation Oscillator with a –162dB FOM
Paul F. J. Geraedts, Ed van Tuijl, Eric A. M. Klumperink,
Gerard J. M. Wienk, Bram Nauta University of Twente, Enschede, Netherlands Both ring oscillators and relaxation oscillators are subsets of RC oscillators featuring large tuning ranges and small areas. Figure 19.5.1 shows
ISSCC 2008 Session 19 Clocking & PLLs
A 0.5-to-480MHz Self-Referenced CMOS Clock Generator with 90ppm Total Frequency Error and Spread-Spectrum Capability
Michael S. McCorquodale1, Scott M. Pernia1, Justin D. O’Day1,
Gordy Carichner1, Eric Marsman1, Nam Nguyen2, Sundus Kubba1, Si Nguyen2, Jon Kuhn1, Richard B. Brown3 1 Mobius Microsystems, Detroit, MI, 2Mobius Microsystems, Sunnyvale, CA University of Utah, Salt Lake City, UT 3 The q
ISSCC 2008 Session 19 Clocking & PLLs
A Temperature-Compensated Digitally-Controlled Crystal Pierce Oscillator for Wireless Applications
Shayan Farahvash, Chee Quek, Monica Mak
Sirenza Microdevices, San Jose, California The traditional analog approach for frequency control of a crystal oscillator (XO) uses a varactor embedded into the structure of the XO to tune its frequency. This method requi
ISSCC 2008 Session 2 Image Sensors
A 128×128 Single-Photon Imager with on-Chip Column-Level 10b Time-to-Digital Converter Array Capable of 97ps Resolution
Cristiano Niclass, Claudio Favi, Theo Kluter, Marek Gersbach, Edoardo Charbon
medical sciences and computer vision, just to name a few. Deep sub-nanosecond timing resolution, in combination with high sensitivity, is becoming increasingly important in a number of imaging methods. Non solid-state de
Ecole Polytechnique Fédérale de Lausanne (EPFL), Lausanne, Switzerland
ISSCC 2008 Session 2 Image Sensors
A CMOS Image Sensor with a Buried-Channel Source Follower
Xinyang Wang1, Martijn F. Snoeij1, 2, Padmakumar R. Rao1,
Adri Mierop3, Albert J.P. Theuwissen1, 4 1 Delft University of Technology, Delft, Netherlands Texas Instruments, Erlangen, Germany 3 DALSA Semiconductors, Eindhoven, Netherlands 4 Harvest Imaging, Bree, Belgium 2 This pa
ISSCC 2008 Session 2 Image Sensors
A 5000S/s Single-Chip Smart Eye-Tracking Sensor
Dongsoo Kim, Jihyun Cho, Seunghyun Lim, Dongmyung Lee, Gunhee Han
user gazes. Infrared (IR) light is commonly used in an eye tracker because it eliminates the influence of ambient illumination and improves the discrepancy between the pupil and the white area in the eye [1]. With the IR
Yonsei University, Seoul, Korea An eye tracker is a system that acquir
ISSCC 2008 Session 2 Image Sensors
A 3MPixel Multi-Aperture Image Sensor with 0.7µm Pixels in 0.11µm CMOS
Keith Fife, Abbas El Gamal, H.-S. Philip Wong
Conventional image sensors have improved with technology scaling mainly by reducing pixel size to increase spatial resolution [1,2]. As resolution approaches the limits of existing optics, is there much to gain from furt
Stanford University, Stanford, CA
ISSCC 2008 Session 2 Image Sensors
A 140dB-Dynamic-Range MOS Image Sensor with In-Pixel Multiple-Exposure Synthesis
Takayoshi Yamada, Shigetaka Kasuga, Takahiko Murata, Yoshihisa Kato
applications. In these applications, a dynamic range of 100dB is generally required, which is far above the dynamic range of conventional image sensors, typically 60dB [1]. Generally, in order to meet the above requireme
Matsushita Electric Industrial, Osaka, Japan Wide dynamic-range image
ISSCC 2008 Session 2 Image Sensors
A White-RGB CFA-Patterned CMOS Image Sensor with Wide Dynamic Range
Yoshitaka Egawa, Nagataka Tanaka, Nobuhiro Kawai, Hiromichi Seki,
mobile phone cameras. But, when very small pixel sizes are used, the sensor SNR is limited by photon shot noise. In order to improve the sensor SNR Honda [1] and Luo [2] proposed the use of a sensor with a white (W) pixe
Akira Nakao, Hiroto Honda, Yoshinori Iida, Makoto Monoi Toshiba, Kanag
ISSCC 2008 Session 2 Image Sensors
A 3.6pW/frame·pixel 1.35V PWM CMOS Imager with Dynamic Pixel Readout and no Static Bias Current
Keiichiro Kagawa1, 2, Sanshiro Shishido1, Masahiro Nunoshita1, Jun Ohta1, 1
compatible with deep submicron logic circuits enables new imager applications, such as disposable medical cameras and autonomous wireless security cameras on a chip. Pulse width modulation (PWM) [1-2] is promising for th
Nara Institute of Science and Technology, Ikoma, Japan Osaka Universit
ISSCC 2008 Session 2 Image Sensors
A CMOS Image Sensor Integrating ColumnParallel Cyclic ADCs with On-Chip Digital Error Correction Circuits
Shoji Kawahito1, Jong-Ho Park2, Keigo Isobe2, Suhaidi Shafie1,
ADCs with high 14b or more of resolution to obtain sufficient image quality after the data pass through the color processing pipeline. A columnparallel ADC in CMOS image sensors helps to enable high-speed readout of high
Tetsuya Iida1, Takashi Mizota3 1 Shizuoka University, Hamamatsu, Japan
ISSCC 2008 Session 2 Image Sensors
A 2Mpixel 1/4-inch CMOS Image Sensor with Enhanced Pixel Architecture for Camera Phones and PC Cameras
Jørgen Moholt1, Trygve Willassen1, John Ladd2, Xiaofeng Fan2, Dean Gans2
Micron, Oslo, Norway, 2Micron, Boise, ID This paper presents performance data for a second-generation, 2Mpixel, 1/4-inch CMOS image sensor with state-of-the-art pixel technology that targets camera phones, PC cameras, PD
ISSCC 2008 Session 2 Image Sensors
Low-Crosstalk and Low-Dark-Current CMOS Image-Sensor Technology Using a Hole-Based Detector
Eric Stevens1, Hirofumi Komori2, Hung Doan1, Hiroaki Fujita1,
Jeffery Kyan1, Christopher Parks1, Gang Shi1, Cristian Tivarus1, Jian Wu1 1 Eastman Kodak, Rochester, NY, 2Eastman Kodak, Yokohama, Japan As the pixel size of CMOS image sensors (CIS) shrink, problems associated with cro
ISSCC 2008 Session 21 Memory
A 153Mb-SRAM Design with Dynamic Stability Enhancement and Leakage Reduction in 45nm High-κ Metal-Gate CMOS Technology
Fatih Hamzaoglu1, Kevin Zhang1, Yih Wang1, Hong Jo Ahn1,
drive the increase of on-die memory density to meet performance needs in various applications such as microprocessors. Meanwhile, the device variation and leakage are increasing as the miniaturization of the transistor c
Uddalak Bhattacharya1, Zhanping Chen1, Yong-Gee Ng1, Andrei Pavlov1, K
ISSCC 2008 Session 21 Memory
A 450ps Access-Time SRAM Macro in 45nm SOI Featuring a Two-Stage Sensing-Scheme and Dynamic Power Management
Harold Pilo1, Vinod Ramadurai1, Geordie Braceras1, John Gabric1,
45nm SOI technology [1]. The macro is adapted for use as the principal growable embedded-SRAM block in a 45nm ASIC library. We describe a two-stage, body-contacted sensing scheme that, among other improvements, achieves
Steve Lamphier1, Yue Tan2 1 IBM, Essex Junction, VT, 2IBM, Hopewell Ju
ISSCC 2008 Session 21 Memory
A High-Density 45nm SRAM Using Small-Signal Non-Strobed Regenerative Sensing
Naveen Verma, Anantha P. Chandrakasan
High-density SRAMs are a primary contributor to the dramatic cost reductions and expanding features of ICs every technology node. Unfortunately, their small bit-cell devices have large variation, and the ensuing degradat
Massachusetts Institute of Technology, Cambridge, MA
ISSCC 2008 Session 21 Memory
A Single-Power-Supply 0.7V 1GHz 45nm SRAM with An Asymmetrical Unit-β-ratio Memory Cell
A. Kawasumi1, T. Yabe1, Y. Takeyama1, O. Hirabayashi1, K. Kushida1,
A. Tohata2, T. Sasaki1, A. Katayama1, G. Fukano1, Y. Fujimura1, N. Otsuka1 1 Toshiba Semiconductor, Kawasaki, Japan Toshiba Microelectronics, Kawasaki, Japan 2 A single-power supply 64kB SRAM is fabricated in a 45nm bulk
ISSCC 2008 Session 21 Memory
65nm Low-Power High-Density SRAM Operable at 1.0V under 3σ Systematic Variation Using Separate Vth Monitoring and Body Bias for NMOS and PMOS
Masanao Yamaoka1, Noriaki Maeda2, Yasuhisa Shimazaki2, Kenichi Osada1
Hitachi, Tokyo, Japan, 2Renesas Technology, Tokyo, Japan Increasing Vth variation is becoming a serious problem in SoCs. Especially in SRAM, Vth variation has a critical impact on operating margins. Self-repairing SRAM [
ISSCC 2008 Session 21 Memory
A 100nm Double-Stacked 500MHz 72Mb SeparateI/O Synchronous SRAM with Automatic Cell-Bias Scheme and Adaptive Block Redundancy
Kyomin Sohn, Young-Ho Suh, Young-Jae Son, Dae-Sik Yim,
Kang-Young Kim, Dae-Gi Bae, Ted Kang, Hoon Lim, Soon-Moon Jung, Hyun-Geun Byun, Young-Hyun Jun, Kinam Kim Samsung Electronics, Hwasung, Korea As multi-core processors become mainstream, the demand for high-density cache
ISSCC 2008 Session 21 Memory
A 32kb 10T Subthreshold SRAM Array with BitInterleaving and Differential Read Scheme in 90nm CMOS
Ik Joon Chang1, Jae-Joon Kim2, Sang Phill Park1, Kaushik Roy1, 1
J. Watson, Yorktown Heights, NY 2 For robust subthreshold SRAMs, 8T or 10T subthreshold SRAMs based on single-ended read sensing have been proposed [1-3]. While the schemes in [1-3] improve the read stability and writabi
Purdue University, West Lafayette, IN, IBM T
ISSCC 2008 Session 21 Memory
An Adaptively Dividable Dual-Port BiTCAM for Virus-Detection Processors in Mobile Devices
Chao-Ching Wang, Chieh-Jen Cheng, Tien-Fu Chen, Jinn-Shyan Wang
Network security is in high demand because of increasing network attacks. As mobile devices have limited CPU power, dedicated hardware is required to provide sufficient virus detection performance with a small energy cos
National Chung-Cheng University, Chia-Yi, Taiwan
ISSCC 2008 Session 22 Other
Razor II: In Situ Error Detection and Correction for PVT and SER Tolerance
David Blaauw1, Sudherssen Kalaiselvan2, Kevin Lai1, Wei-Hsiang Ma1,
Performance variation due to PVT uncertainty has led to an increased interest in adaptive designs. Traditional methods for adaptive design have used so-called canary circuits that mimic the critical-path delay of the act
Sanjay Pant1, Carlos Tokunaga1, Shidhartha Das3, David Bull3 1 Univers
ISSCC 2008 Session 22 Other
Energy-Efficient and Metastability-Immune TimingError Detection and Instruction-Replay-Based Recovery Circuits for Dynamic-Variation Tolerance
Keith A. Bowman, James W. Tschanz, Nam Sung Kim, Janice C. Lee,
Chris B. Wilkerson, Shih-Lien L. Lu, Tanay Karnik, Vivek K. De Intel, Hillsboro, OR Microprocessor clock frequency (FCLK) is traditionally determined based on maximum supply voltage (Vcc) droop and temperature specificat
ISSCC 2008 Session 22 Other
A Process-Variation-Tolerant Floating-Point Unit with Voltage Interpolation and Variable Latency
Xiaoyao Liang, David Brooks, Gu-Yeon Wei
Process variation will greatly impact the power and performance of future microprocessors. Design approaches based on multiple supply or threshold voltage assignment provide techniques to statically tune critical path de
Harvard University, Cambridge, MA
ISSCC 2008 Session 22 Other
A Commercial Field-Programmable Dense eFUSE Array Memory with 99.999% Sense Yield for 45nm SOI CMOS
Greg Uhlmann1, Tony Aipperspach1, Toshiaki Kirihata2,
Chandrasekharan, Kothandaraman2, Yan Zun Li2, Chris Paone1, Brian Reed1, Norman Robson2, John Safran2, David Schmitt1, Subramanian Iyer2 1 IBM, Rochester, MN IBM, East Fishkill, NY 2 A nickel silicide polysilicon eFUSE p
ISSCC 2008 Session 22 Other
An All-Digital On-Chip Process-Control Monitor for Process-Variability Measurements
Fabian Klass, Ashish Jain, Greg Hess, Brian Park
P. A. Semi, Santa Clara, CA Process variability has become a major challenge in nanometer technologies. The trend is driven by Moore’s law, low-power requirements (i.e., low VDD), and shrinking device geometries. Underst
ISSCC 2008 Session 22 Other
Compact In-Situ Sensors for Monitoring NegativeBias-Temperature-Instability Effect and Oxide Degradation
E. Karl, P. Singh, D. Blaauw, D. Sylvester
Semiconductor reliability is a growing issue as device critical dimensions shrink and integration levels continue to grow at a rapid pace. Aggressive oxide thickness scaling has led to large vertical electric fields in M
University of Michigan, Ann Arbor, MI
ISSCC 2008 Session 22 Other
A Completely Digital On-Chip Circuit for Local–Random-Variability Measurement
Rahul Rao, Keith A. Jenkins, Jae-Joon Kim
Accurate characterization and measurement of local variation in threshold voltage (Vt) of closely spaced devices is essential for process optimization, yield enhancement and design of analog circuits in current technolog
IBM T. J. Watson, Yorktown Heights, NY
ISSCC 2008 Session 22 Other
1200µm2 Physical Random-Number Generators Based on SiN MOSFET for Secure Smart-Card Application
Mari Matsumoto, Shinichi Yasuda, Ryuji Ohba, Kazutaka Ikegami,
financial transactions and the transfer of confidential information. Small circuits for high-level information security have to be implemented in these chips. These secure circuits thus require a small ph-RNG (physical r
Tetsufumi Tanamoto, Shinobu Fujita Toshiba, Kawasaki, Japan Secure dig
ISSCC 2008 Session 22 Other
A Charge-Injection-Based Active-Decoupling Technique for Inductive-Supply-Noise Suppression
Sanjay Pant, David Blaauw
Aggressive scaling and increasing clock frequency have exacerbated inductive (Ldi/dt) supply noise, decreasing the robustness of power delivery networks. Ldi/dt is further aggravated by commonly used power-reduction tech
University of Michigan, Ann Arbor, MI
ISSCC 2008 Session 23 Memory
A 34MB/s-Program-Throughput 16Gb MLC NAND with All-Bitline Architecture in 56nm
Raul Cernea1, Long Pham1, Farookh Moogat1, Siu Chan1, Binh Le1, Yan Li1,
Shouchang Tsao1, Tai-Yuan Tseng1, Khanh Nguyen1, Jason Li1, Jayson Hu1, Jong Park1, Cynthia Hsu1, Fanglin Zhang1, Teruhiko Kamei1, Hiroaki Nasu1, Phil Kliza1, Khin Htoo1, Jeffrey Lutze1, Yingda Dong1, Masaaki Higashitani
ISSCC 2008 Session 23 Memory
A 4b/Cell 8Gb NROM Data-Storage Memory with Enhanced Write Performance
Ran Sahar1, Avi Lavan1, Eran Geyari1, Amit Berman1, Itzic Cohen1, Ori Tirosh1,
Kobi Danon1, Yair Sofer1, Yoram Betser1, Amichai Givant1, Alexander Kushnarenko1, Yaal Horesh1, Ron Eliyahu1, Eduardo Maayan1, Boaz Eitan1, Wang Pei Jen2, Yan Feng2, Lin Ching Yao2, Kwon Yi Jin2, Kwon Sung Woo2, Cai En J
ISSCC 2008 Session 23 Memory
A 45nm Self-Aligned-Contact Process 1Gb NOR Flash with 5MB/s Program Speed
Johnny Javanifard, Tris Tanadi, Hari Giduturi, Kim Loe,
Robert L. Melcher, Shahnam Khabiri, Nicholas T. Hendrickson, Andrew D. Proescholdt, David A. Ward, Mark A. Taylor Intel, Folsom, CA When transitioning to the 45nm process node, undesirable cell effects become many times
ISSCC 2008 Session 23 Memory
A 50nm 8Gb NAND Flash Memory with 100MB/s Program Throughput and 200MB/s DDR Interface
Dean Nobunaga1, Ebrahim Abedifard1, Frankie Roohparvar1,
June Lee1, Erwin Yu1, Allahyar Vahidimowlavi1, Michael Abraham1, Sanjay Talreja2, Rajesh Sundaram2, Rod Rozman2, Luyen Vu1, Chih Liang Chen1, Uday Chandrasekhar1, Rupinder Bains2, Vimon Viajedor1, William Mak1, Munseork