ISSCC 2009 — ISSCC 知识库

ISSCC 2009 Session 19 Analog Circuits

A 65nm CMOS Comparator with Modified Latch to Achieve 7GHz/1.3mW at 1.2V and 700MHz/47µW at 0.6V

Bernhard Goll, Horst Zimmermann

Clocked regenerative comparators, which use positive feedback of a latch to force a fast decision, are used for many applications. In [1] a 10GHz 3-stage comparator in 1.2V 0.11µm CMOS is presented and is designed to ext

Vienna University of Technology, Vienna, Austria

ISSCC 2009 Session 19 Analog Circuits

A 25mA 0.13µm CMOS LDO Regulator with PowerSupply Rejection Better Than −56dB up to 10MHz Using a Feedforward Ripple-Cancellation Technique

Mohamed El-Nozahi, Ahmed Amer, Joselyn Torres, Kamran Entesari, Edgar Sánchez-Sinencio

block in portable communication systems for power management ICs. The LDO usually comes after a switching DC-DC converter to reduce the output ripples and provide a regulated voltage source for noise-sensitive blocks. Fo

Texas A&M University, College Station, TX Low drop-out (LDO) linear re

ISSCC 2009 Session 19 Analog Circuits

A sub-1V Bandgap Voltage Reference in 32nm FinFET Technology

A.J. Annema1, P. Veldhorst1, G. Doornbos2, B. Nauta1, 1

likely the successor would be the FinFET. The FinFET is an ultra-thin body multi-gate MOS transistor with among other characteristics a much higher voltage gain compared to a conventional bulk MOS transistor [1]. Bandgap

University of Twente, Enschede, Netherlands NXP-TSMC Research Center,

ISSCC 2009 Session 19 Analog Circuits

A 90nm CMOS CT BPF for Bluetooth Transceivers with DT 1b-Switched-Resistor Cutoff-Frequency Control

Hideaki Majima, Mototsugu Hamada

In this paper, a scheme for tuning cutoff-frequency of filters is presented. Instead of using a multibit resistor bank, a 1b switched-resistor structure operating at 200MHz is utilized. The effective RC time constant is

Toshiba, Kawasaki, Japan

ISSCC 2009 Session 19 Analog Circuits

A 1.25mW 75dB-SFDR CT Filter with In-Band Noise Reduction

Antonio Liscidini, Alberto Pirola, Rinaldo Castello

In a direct-conversion wireless receiver the baseband filter should be able to handle large blockers, resulting in a very challenging spurious free dynamic range (SFDR) requirement. In particular, the noise added in-band

University of Pavia, Pavia, Italy

ISSCC 2009 Session 2 Image Sensors

A 4-Side Tileable Back Illuminated 3D-Integrated Mpixel CMOS Image Sensor

Vyshnavi Suntharalingam1, Robert Berger1, Stewart Clark2,

Jeffrey Knecht1, Andrew Messier1, Kevin Newcomb1, Dennis Rathman1, Richard Slattery1, Antonio Soares1, Charles Stevenson1, Keith Warner1, Douglas Young1, Lin Ping Ang3, Barmak Mansoorian3, David Shaver1 1 MIT Lincoln Lab

ISSCC 2009 Session 2 Image Sensors

A 4-Channel 20-to300 Mpixel/s Analog Front-End with Sampled Thermal Noise Below kT/C for Digital SLR Cameras ply nodes VDD and VSS caused by parasitic inductance, limiting crosstalk. Also, the floating current mirror formed by MN1 and MN2 allows the bias current to be easily optimized by the nonlinear bias generator described earlier.

Analog Devices, Wilmington, MA

Analog Devices, Beijing, China With this new reference buffer, measured crosstalk exceeds -85dB. A fullscale step input is applied to the aggressor channel, and other channels are measured with inputs grounded. Channel m

Analog Devices, Tokyo, Japan

ISSCC 2009 Session 2 Image Sensors

A 1/2.5-inch 8Mpixel CMOS Image Sensor with a Staggered Shared-Pixel Architecture and an FDBoost Operation

Nagataka Tanaka, Junji Naruse, Akiko Mori, Ryuta Okamoto,

architectures have previously been proposed [1-3]. However, the use of conventional shared-pixel architectures leads to a Gr/Gb sensitivity imbalance because the Gr pixel and the Gb pixel have a different layout structur

Hirofumi Yamashita, Makoto Monoi Toshiba Semiconductor, Yokohama, Japa

ISSCC 2009 Session 2 Image Sensors

An SoC Combining a 132dB QVGA Pixel Array and a 32b DSP/MCU Processor for Vision Applications

Pierre-François Rüedi, Pascal Heim, Stève Gyger, François Kaess,

optical front-end, and a data representation that is as independent as possible from the illumination level. Furthermore, combining an optical front-end and a processor on the same chip enables a single-chip vision syste

Claude Arm, Ricardo Caseiro, Jean-Luc Nagel, Silvio Todeschini CSEM, N

ISSCC 2009 Session 2 Image Sensors

A Charge-Multiplication CMOS Image Sensor Suitable for Low-Light-Level Imaging

Ryu Shimizu, Mamoru Arimoto, Hayato Nakashima, Kaori Misawa,

Kazuhiro Suzuki, Toshikazu Ohno, Yugo Nose, Keisuke Watanabe, Tatsushi Ohyama, Kuniyuki Tani Sanyo Electric, Gifu, Japan Charge multiplication using impact ionization [1] was proposed in the 1980s to improve the sensitiv

ISSCC 2009 Session 2 Image Sensors

A Dual-Conversion-Gain Video Sensor Dewarping and Overlay on a Single Chip with

Anthony Huggett1, Chris Silsby2, Sergi Cami1, Jeff Beck2, 1

Aptina Imaging, Bracknell, United Kingdom Aptina Imaging, Corvallis, OR 2 Automotive sensors such as video-reversing cameras demand excellent lowlight performance whilst also being able to handle full sunlight. Furthermo

ISSCC 2009 Session 20 Sensors

A 1.05V 1.6mW 0.45°C 3σ-Resolution ∆Σ-Based Temperature Sensor with Parasitic-Resistance Compensation in 32nm CMOS

Y. William Li, Hasnain Lakdawala, Arijit Raychowdhury, Greg Taylor, K. Soumyanath

Intel, Hillsboro, OR In the multicore era, thermal/power management is essential in order to meet platform-performance and energy-efficiency requirements. Accurate temperature measurements are required to reliably maximi

ISSCC 2009 Session 20 Sensors

A CMOS Smart Temperature Sensor with a BatchCalibrated Inaccuracy of ±0.25°C (3σ) from -70°C to 130°C

André L. Aita1,2, Michiel A. P. Pertijs3, Kofi A. A. Makinwa1, Johan H. Huijsing1

Delft University of Technology, Delft, Netherlands Federal University of Santa Maria, Santa Maria, Brazil 3 Holst Centre, Eindhoven, Netherlands 2 A major contributor to the total cost of precision CMOS temperature senso

ISSCC 2009 Session 20 Sensors

An Interface for a 300°/s Capacitive 2-Axis MicroGyroscope with Pseudo-CT Readout

Lasse Aaltonen1, Timo Speeti1, Mikko Saukoski1,2, Kari Halonen1, 1

The widespread use of capacitive MEMS vibratory gyroscopes is powerfully driven by low cost [1]; this is partly determined by factors such as die area and the number of necessary external components. Important properties

Helsinki University of Technology, Espoo, Finland ELMOS Semiconductor,

ISSCC 2009 Session 20 Sensors

An Instrument-on-Chip for Impedance Measurements on Nanobiosensors with attoFarad Resolution

Fabio Gozzini, Giorgio Ferrari, Marco Sampietro

Impedance measurements play a fundamental role in biotechnology, serving both as an investigation tool and as a direct detection technique. Tracking impedance over time is extensively used for spatial monitoring, imaging

Politecnico di Milano, Milan, Italy

ISSCC 2009 Session 20 Sensors

A Sub-pA ∆Σ Current Amplifier for Single-Molecule Nanosensors

Marco Bennati1, Federico Thei1, Michele Rossi2, Marco Crescentini1,

University of Milano-Bicocca, Milano, Italy 2 Current readout has been a known technique since the inception of electronic sensors and is widely used, for example, in radiation detectors, impedance spectroscopy, and mech

Gennaro D’Avino3, Andrea Baschirotto3,4, Marco Tartagni1 1 University

ISSCC 2009 Session 20 Sensors

A Compact CMOS MEMS Microphone with 66dB SNR

Jelena Čitaković1,2, Per F. Høvesten1, Gino Rocca1, Aart van Halteren3,

Pirmin Rombach1, Lars J. Stenberg1, Pietro Andreani4, Erik Bruun2 Pulse MEMS, Roskilde, Denmark Technical University of Denmark, Lyngby, Denmark 3 Pulse Advanced Acoustics, Amsterdam, Netherlands 4 Lund University, Lund,

ISSCC 2009 Session 20 Sensors

A 2×32 Range-Finding Sensor Array with PixelInherent Suppression of Ambient Light up to 120klx

Gerald Zach, Horst Zimmermann

Real-time 3D imaging has reached a state of development where several fields of application are possible, such as factory automation, consumer electronics, security, and robotics. The first commercial products have alrea

Vienna University of Technology, Vienna, Austria

ISSCC 2009 Session 20 Sensors

A 0.25µm Logarithmic CMOS Imager for EmissivityCompensated Thermography

Franz X. Hutter, Daniel Brosch, Heinz-Gerd Graf, Wolfram Klingler,

Markus Strobel, Joachim N. Burghartz Institute for Microelectronics, Stuttgart, Germany Challenges in the design of solid-state imagers for industrial measurement and control include: high image resolution, wide temperat

ISSCC 2009 Session 22 RF & Wireless

A 0.13µm CMOS Power Amplifier with Ultra-Wide Instantaneous Bandwidth for Imaging Applications

Jonathan Roderick, Hossein Hashemi

The increased interest in Ultra-WideBand (UWB) impulse-based systems for high-resolution imaging applications [1] has created a demand for mediumpower linear amplifiers capable of transmitting such signals (FCC limits pe

University of Southern California, Los Angeles, CA

ISSCC 2009 Session 22 RF & Wireless

An Octave-Range Watt-Level Fully Integrated CMOS Switching Power Mixer Array for Linearization and Back-Off Efficiency Improvement

Shouhei Kousai1, 2, Ali Hajimiri1

Non-constant envelope modulation schemes have become commonplace in cellular applications due to their higher spectral efficiency. Linear PAs driven by an RF transmitter are usually used to generate these signals faithfu

California Institute of Technology, Pasadena, CA, 2Toshiba, Kawasaki,

ISSCC 2009 Session 22 RF & Wireless

A Single-Chip Highly Linear 2.4GHz 30dBm Power Amplifier in 90nm CMOS

Debopriyo Chowdhury1, Christopher D. Hull2, Ofir B. Degani2,

Pankaj Goyal2, Yanjie Wang1, Ali M. Niknejad1 University of California, Berkeley, CA Intel, Hillsboro, OR In CMOS PAs, AM-PM distortion is also a major contributor to EVM. To reduce this, a PMOS-based capacitive compensa

ISSCC 2009 Session 22 RF & Wireless

A 60GHz-Band 1V 11.5dBm Power Amplifier with 11% PAE in 65nm CMOS

Wei L. Chan1, John R. Long1, Marco Spirito1, John J. Pekarik2, 1

output power in Fig. 22.4.3. The maximum saturated output power is 11.5dBm, with a peak PAE close to 11% at 9dBm output power. The measured small-signal gain is also slightly higher than given in Fig. 22.4.2 at 58GHz, as

Delft University of Technology, Delft, Netherlands IBM, Burlington, VT

ISSCC 2009 Session 22 RF & Wireless

50-to-67GHz ESD-Protected Power Amplifiers in Digital 45nm LP CMOS

Kuba Raczkowski1,2, Steven Thijs1,2, Walter De Raedt1, Bart Nauwelaers2,

shown that downscaled CMOS is a serious technology candidate to implement transceivers for high-data-rate wireless communication around 60GHz [1,2]. A low-cost implementation is the combination of the digital part with t

Piet Wambacq1,3 1 IMEC, Leuven, Belgium, KU Leuven, Leuven, Belgium, 3

ISSCC 2009 Session 22 RF & Wireless

A CMOS Adaptive Antenna-Impedance-Tuning IC Operating in the 850MHz-to-2GHz Band

Hang Song, Bertan Bakkaloglu, James T. Aberle

Adaptive antenna-tuning units (AATUs) provide broadband dynamic tuning to widely-varying antenna impedances caused by the changes in operating frequencies and unpredictable environmental factors. AATUs are becoming a cri

Arizona State University, Tempe, AZ

ISSCC 2009 Session 22 RF & Wireless

A Tunable Integrated Duplexer with 50dB Isolation in 40nm CMOS

M. Mikhemar1, H. Darabi1, A. Abidi2, 1

frequency-selective filters for isolation. The stringent isolation requirements prohibit the integration of RF duplexers on silicon and particularly in CMOS technology. However, CMOS technology offers superior tuning and

Broadcom, Irvine, CA University of California, Los Angeles, CA 2 Moder

ISSCC 2009 Session 23 Clocking & PLLs

A 1MHz-Bandwidth Type-I ∆Σ Fractional-N Synthesizer for WiMAX Applications

Hiva Hedayati1, Bertan Bakkaloglu1, Waleed Khalil2

Intel, Chandler, AZ 1 2 A major source of close-in phase noise in ∆Σ fractional-N frequency synthesizers is noise-folding due to the nonlinear behavior of the combined phasefrequency detector (PFD)/charge-pump (CP) circu

Arizona State University, Tempe, AZ

ISSCC 2009 Session 23 Clocking & PLLs

A 2.2GHz 7.6mW Sub-Sampling PLL with −126dBc/Hz In-Band Phase Noise and 0.15psrms Jitter in 0.18µm CMOS

Xiang Gao1, Eric A. M. Klumperink1, Mounir Bohsali2, Bram Nauta1

University of Twente, Enschede, The Netherlands National Semiconductor, Santa Clara, CA 2 A clock with low phase-noise/jitter is a prerequisite for high-performance ADCs, wireline and optical data links and radio transce

ISSCC 2009 Session 23 Clocking & PLLs

An Edge-Missing Compensator for Fast-Settling Wide-Locking-Range PLLs

Ting-Hsu Chien1, Chi-Sheng Lin1, Ying-Zong Juang1,

In this situation, the output of OAI gate switching from ‘0’ to ‘1’ indicates the occurrence of current compensation. When an EXT missing edge occurs, the DC=’0’ implies the amount of E recording in full adder is decreme

Chun-Ming Huang1, Chin-Long Wey1,2 National Chip Implementation Center

ISSCC 2009 Session 23 Clocking & PLLs

A 975-to-1960MHz Fast-Locking Fractional-N Synthesizer with Adaptive Bandwidth Control and 4/4.5 Prescaler for Digital TV Tuners

Lei Lu1,2, Zhichao Gong1,2, Youchun Liao2, Hao Min1, Zhangwen Tang1

Ratio Microelectronics, Shanghai, China 1 2 There is a high demand for high-performance tuners to meet the digital video broadcasting-terrestrial (DVB-T) standard. Often the DVB-T tuners employ a double-conversion zero-I

Fudan University, Shanghai, China

ISSCC 2009 Session 23 Clocking & PLLs

A 0.4-to-1.6GHz Low-OSR ∆Σ DLL with SelfReferenced Multiphase Generation

Xueyi Yu1, Woogeun Rhee1, Zhihua Wang1, Jung-Bae Lee2, Changhyun Kim2

Tsinghua University, Beijing, China Samsung Electronics, Hwasung, Korea 2 As data rate of wireline applications increases, clock skew becomes a significant portion of the overall timing margin and directly affects the BE

ISSCC 2009 Session 23 Clocking & PLLs

A Leakage-Suppression Technique for Phase-Locked Systems in 65nm CMOS

Chao-Ching Hung, Shen-Iuan Liu

In nanoscale CMOS processes, the leakage current [1,2] is becoming one of the important issues to cope with for high-performance analog and mixed-signal integrated circuits. For digital circuits, the leakage current resu

National Taiwan University, Taipei, Taiwan

ISSCC 2009 Session 23 Clocking & PLLs

23. 7 A Precision Relaxation Oscillator with a SelfClocked Offset-Cancellation Scheme for Implantable Biomedical SoCs

Kunil Choe1, Olivier D. Bernal1, David Nuttman2, Minkyu Je1

Physical Logic, Bnei Brak, Israel 1 that there is no current flow through the selected transistor Mn. This eliminates calibration nonlinearity due to the parasitic resistances of the switch transistors which are placed i

Institute of Microelectronics, Singapore, Singapore

ISSCC 2009 Session 23 Clocking & PLLs

An On-Chip CMOS Relaxation Oscillator with Power Averaging Feedback Using a Reference Proportional to Supply Voltage

Yusuke Tokunaga, Shiro Sakiyama, Akinori Matsumoto, Shiro Dosho

Recently, on-chip reference oscillators are required for low-cost single-chip applications including biomedical sensors, microcomputers, high-speed interfaces such as DDR I/F and HDMI (for initial negotiation), and SoCs.

Panasonic, Osaka, Japan