2010

For the applications requiring medium-to-high resolution ADCs, the pipelined architecture is considered to be the most optimal structure in terms of power consumption and area. With range overlap and redundant bit at eac

Scaling in CMOS technologies has made the application of traditional opamp topologies increasingly difficult. In the face of decreasing voltage headroom and intrinsic device gain, designers have employed techniques such

longer battery life and lower cost. Achieving low out–of-band noise (OBN) is one of the key elements in designing inexpensive, low-power and robust audio DACs. Lowering OBN reduces the sensitivity to circuit mismatch, gl

Kwok Ping Ng, Bo Gao, Howard Cam Luong, Amine Bermak, Mansun Chan, Wing-Hung Ki, Chi-Ying Tsui, Matthew Ming-Fai Yuen Hong Kong University of Science and Technology, Hong Kong, China A system-on-chip passive UHF RFID tag

Salvatore Drago1,3, Domine M. W, Leenaerts1, Bram Nauta3 1 NXP Semiconductors, Eindhoven, Netherlands Delft University of Technology, Delft, Netherlands 3 University of Twente, Enschede, Netherlands 2 This paper describe

based on the thermal diffusivity of silicon. Its digital output is insensitive to both process spread and packaging stress and is a near-linear function of absolute temperature. The sensor’s accuracy is mainly limited by

L.Richard Carley1, Jonathan C. Jensen2 1 Carnegie Mellon University, Pittsburgh, PA Intel, Hillsboro, OR 3 Intel, Haifa, Israel 2 Multi-radio (3G/4G/GPS) mobile communication devices impose stringent requirements (<1ppm)

Georgia Institute of Technology, Atlanta, GA Oklahoma State University, Tulsa, OK 2 The frequency reference oscillator is a pivotal block in modern radio transceivers. Currently, modern transceivers rely on off-chip low

which allows the resonances of the element to be efficiently damped and permits, for example, an open-loop readout of the element. If the accelerometer is required to attain very low Brownian noise levels or packaged tog

United Kingdom 2 Short optical pulses are required for diagnostic techniques in life sciences such as fluorescence lifetime imaging, which can be used for quantitative detection of ion concentrations, oxygen and fluoresc

Hideaki Yamamoto, Yousuke Hagiwara, Tetsuya Fujita, Manabu Watanabe, Takayoshi Shimazawa, Yasuo Ohara, Takashi Miyamori, Mototsugu Hamada, Masafumi Takahashi, Yukihito Oowaki Toshiba, Kawasaki, Japan Today’s multimedia m

Himanshu Kaul, Farhana Sheikh, Rajaraman Ramanarayanan, Suresh Srinivasan, Ram Krishnamurthy, Shekhar Borkar Intel, Hillsboro, OR Computationally intensive DSP/media processing applications require specialized hardware a

applications are emerging. The first involves more vivid perceptual experience and is leading to the next generation of TV specifications – Quad Full HD (QFHD, 4096×2160p) and 3D/multi-view TV. The second is the scalable

challenges: (1) the large number of features to process requires high computational power, and (2) false matches from background clutter can degrade recognition accuracy. Previously, saliency based bottom-up visual atten

Takayuki Gyoten1, Tetsu Nishijima1, Hiroyuki Yamasaki1, Yuta Imai2, Masakatsu Ishizaki1, Takeshi Kumaki2, Yoshihiro Okuno1, Tetsushi Koide2, Hans Jürgen Mattausch2, Kazutami Arimoto1 1 Renesas Technology, Itami, Japan Hi

Graphics processing generates pixels from descriptors, while vision generates descriptors from pixels [1]. Since augmented reality (AR) requires both graphics and vision abilities (Fig. 18.6.1), we report a unified proce

versatile multimedia applications with semantic processing abilities. Realtime applications, such as face detection, facial-expression recognition, scene analysis [2] and object recognition [3], have become indispensable

Gregory Fredeman2, Michael Sperling2, Abraham Mathews3, William Reohr4, Kavita Nair2, Nianzheng Cao2 1 IBM, Essex Junction, VT IBM, Poughkeepsie, NY 3 IBM, Austin, TX 4 IBM T. J. Watson, Yorktown Heights, NY 2 Logic-base

Wolfgang Penth1, Thomas Froehnel1, Stefan Buettner1, Otto Torreiter1, Martin Eckert1, Jose Paredes2, David Hrusecky2, David Ray2, Miles Canada3 1 IBM, Boeblingen, Germany IBM, Austin, TX 3 IBM, Burlington, VT 2 Increasin

performance, and density requirements as Moore’s law continues to drive CMOS technology scaling. Due to process variation, SRAM bitcell design margin continues to shrink in scaled technologies and conventional SRAM is no

Atsushi Kawasumi, Yasuhisa Takeyama, Keiichi Kushida, Gou Fukano, Akira Katayama, Yusuke Niki, Tomoaki Yabe Toshiba Semiconductor, Kawasaki, Japan This paper presents a configurable SRAM for low-voltage operation with co

J. Watson, Yorktown Heights, NY There is a need for large embedded memory that operates over a wide range of supply voltage compatible with the limits of static CMOS logic that also minimizes standby power [1,2]. A 512kb

19.6.1) is commonly used in single-VCC microprocessor core for its performance critical low-level caches and multi-ported register-file arrays

J. Watson, Yorktown Heights, NY 2 It is desirable to observe the cell read current at lower cell supplies. Lowering the array supply voltage VCELL can magnify the effect of read disturbance that raises the internal node

characteristics reduce the operational margin of SRAM functionality, and several design techniques have been suggested to improve margins [1-3]. However, it is still difficult to achieve low-voltage operation (less than

The phased array is a common technique where multiple spaced antennas electronically form and scan narrow electromagnetic beams to achieve spatial selectivity. These arrays are also referred to as steering arrays. On the

U. Leuven, Leuven, Belgium 3 Vrije Universiteit Brussel, Brussels, Belgium 2 For high-data-rate wireless communication in the 7GHz band around 60GHz, the IEEE 802.15.3c standard [1] provides channels with a 0.88GHz bandw

independent tuning of both vertical and horizontal polarizations realized in 65nm bulk CMOS is described in this paper. Phased-array transmitters increase the isotropic radiated power of a stand-alone transmitter over a

The ever-increasing demand for higher data rates in communication links has created a need for power amplifiers with large instantaneous bandwidth. Moreover, software-defined radio and smart antenna systems require power

In all-digital phase-locked loops (ADPLLs), the quantization noise introduced by the frequency discretization in the digitally controlled oscillator (DCO) can affect the performance in terms of out-of-band phase noise. I

Flicker noise up-conversion into close-in 1/f3 phase noise is still one of the major issues in the design of CMOS oscillators. Suppression techniques have been recently presented suggesting (i) adoption of a resonant net

Passive RFID technology enables battery-free wearable and implantable sensors with an unlimited lifespan, small size, and sub-gram weight. These properties facilitate advanced biomedical research (such as untethered moni

Sherif Abdalla, Jeremy Witzens, Subal Sahni Luxtera, Carlsbad, CA As data networks scale to meet increasing bandwidth requirements, the shortcomings of copper channels are becoming more apparent. Dispersion, attenuation,

Yonsei University, Seoul, Korea Ewha Womans University, Seoul, Korea 2 Recently, low-cost silicon optoelectronic integrated circuits (OEICs) have been drawing attention for applications in short-distance optical communic

Yasunori Tsukuda1, Yuki Yagishita1, Hironobu Konishi2, Toshiyuki Ogata2, Hisashi Owa1, Taichi Niki1, Kenji Konda1, Masahiro Sato1, Hiroshi Shiroshita1, Takeshi Ogura1, Takayuki Aoki1, Hiroki Kihara1, Sachiya Tanaka1 1 So

Doug Gambetta1, Sujatha Gowder1, Sitaraman Iyer1, Rohit Kumar1, Peter Kwok1, Renuka Krishnamurthy1, Chien-chun Lin1, Ravindran Mohanavelu1, Roan Nicholson1, Jeff Ou1, Marcus Pasquarella1, Kavitha Prasad1, Hendra Rustam1,

power dissipation per Gb/s to less than 1mW/(Gb/s) (i.e., 1pJ/b) has been a long-held goal. Several years ago, the power dissipation of these links was in the range of about 10 to 20mW/(Gb/s). In 2007, Poulton et al. dev

Teva Stone1, Barry Daly1 1 Rambus, Chapel Hill, NC, Rambus, Bangalore, India 2 Source-series-terminated (SST) transmitters consume ¼ the output stage power of CML drivers [1], but their adoption in industry-standard mult

systems span a wide range: from 1-to-2mm on-package links (OPLs) in MCMs, to 25-to-100cm backplanes in server systems. Signaling with optimal power efficiency over such a diverse set of channels requires adaptation of th

The ever growing bandwidth requirement for novel server technologies including multi-core processing, virtualization, and networked storage leads to multichannel Internet connectivity such as 100GbE. Among the proposed s

21.1.3. To allow auto-zeroing of offset and 1/f noise, additional switches are added to allow the amplified offset and 1/f noise of the first stage to be stored on the inter-stage capacitors C1 and C2. Since a full ten b

CMOS technology scaling has opened a pathway to high-performance analogto-digital conversion in the nanometer regime, where switching is preferred over amplifying. Successive-approximation-register (SAR) is one of the co

In 10b SAR ADCs, one of the major design challenges is the large number of capacitors for implementing the capacitor array. A large unit capacitance should be used due to the design constraint of capacitor mismatches and

power efficient ADCs. SAR ADC power scales with CMOS technology because it does not need operational amplifiers, which are getting difficult to design in deeply scaled CMOS. Recent published SAR ADCs have no static curre

with three compensative capacitors can tolerate settling error of at least 12.5% in each bit cycle. Note the precise error tolerance range depends on where the wrong decision occurs. The amplitude of the input signal swi

power-efficient ADCs. Moreover, the power-efficiency should be maintained for a wide range of sampling rates to enable system-level flexibility. Previously, the use of SAR ADCs has been proposed for low-power application

Robert Gibbins, Chris Falt, Philip Flemke, Naim Ben-Hamida, Daniel Pollex, Peter Schvan, Shing-Chi Wang Nortel, Ottawa, Canada Progress in 40Gb/s optical dual- polarization (DP) QPSK systems inspired an idea of 100G tran

the demands for high-density and high-speed imaging have increased drastically. Since CMOS image sensors have the advantages of low power consumption and easy system integration, they have become dominant over CCDs in th

Youngkyun Jeong, Seungjin Lee, Hansoo Lee, Sin-Hwan Lim, Yunseok Han, Jinwoo Kim, Jaecheol Yun, Seogheon Ham, Yun-Tae Lee Samsung Electronics, Yongin, Korea The noise performance of CMOS image sensors has improved signif

A low-noise global shutter CMOS image sensor is a next challenge to expand the market for CMOS image sensors. A low-noise global electronic shutter can be used for various applications such as high-speed imaging, machine