ISSCC 2013
Session 15
Data Converters
A 20b Clockless DAC with Sub-ppm-Linearity 7.5nV/√Hz-Noise and 0.05ppm/°C-Stability
Douglas Chisholm1, Denise T. Lee1 Analog Devices, Edinburgh, United Kingdom, Analog Devices, Wilmington, MA 1 2 DACs without continuous clocking are often favored in applications such as medical imaging and scientific in
ISSCC 2013
Session 15
Data Converters
A 2.4-to-5.2fJ/conversion-step 10b 0.5-to-4MS/s SAR ADC with Charge-Average Switching DAC in 90nm CMOS
Applications of wireless sensor networks and biomedical devices frequently require an ADC with medium resolution (8 to 12b) running at hundreds of kS/s to a few MS/s. Successive-approximation register (SAR) ADCs show con
ISSCC 2013
Session 15
Data Converters
Adaptive Cancellation of Gain and Nonlinearity Errors in Pipelined ADCs
ΔΣ modulators and pipelined ADCs, accurately transferring voltages in sampled-data form, regardless of opamp gain and nonlinearity, has been one of the most challenging issues that analog designers have faced. To date, i
ISSCC 2013
Session 16
Medical & Bio
A Fully Integrated 8-Channel Closed-Loop Neural-Prosthetic SoC for Real-Time Epileptic Seizure Control
Chi Jeng1, Shun-Ting Chang1, Ming-Dou Ker1, Chun-Yu Lin1, Ya-Chun Huang1, Chia-Wei Chou1, Tsun-Yuan Fan1, Ming-Seng Cheng1, Sheng-Fu Liang2, Tzu-Chieh Chien2, Sih-Yen Wu2, Yu-Lin Wang2, Fu-Zen Shaw2, Yu-Hsing Huang2, Chi
ISSCC 2013
Session 16
Medical & Bio
An Implantable 455-Active-Electrode 52-Channel CMOS Neural Probe
Marleen Welkenhuysen1, Wolfgang Eberle1, Carmen Bartic2, Robert Puers2, Refet Firat Yazicioglu1, Georges Gielen2 imec, Heverlee, Belgium, 2KU Leuven, Heverlee, Belgium 1 Several studies have demonstrated that understandi
ISSCC 2013
Session 16
Medical & Bio
A 0.45V 100-Channel Neural-Recording IC with Sub-μW/Channel Consumption in 0.18μm CMOS
Conventional neural-recording systems face limitations in simultaneously achieving a good NEF and low power consumption [1-4]. This is because the input amplifier current consumption is dictated by an input-referred nois
ISSCC 2013
Session 16
Medical & Bio
24-Channel Dual-Band Wireless Neural Recorder with Activity-Dependent Power Consumption
activity from freely behaving animals has become extremely important for basic research in neuroscience. One of the major limitations in this domain arises from the need of a low-power, lightweight, wireless recording un
ISSCC 2013
Session 16
Medical & Bio
A 37.6mm2 1024-Channel High-Compliance-Voltage SoC for Epiretinal Prostheses
Retinal implants elicit light perception for people blinded by photoreceptor loss. Commercialized 60-channel retinal prostheses allow patients to perform simple tasks, but several hundreds to a thousand electrodes are re
ISSCC 2013
Session 16
Medical & Bio
A Fully Intraocular 0.0169mm2/pixel 512-Channel Self-Calibrating Epiretinal Prosthesis in 65nm CMOS
Han-Chieh Chang1, Yu Zhao1, James Weiland2,3, Mark Humayun2,3, Yu-Chong Tai1, Azita Emami-Neyestanak1 California Institute of Technology, Pasadena, CA, Doheny Eye Institute, Los Angeles, CA, 3 University of Southern Cali
ISSCC 2013
Session 16
Medical & Bio
A Near-Field-Communication (NFC) Enabled Wireless Fluorimeter for Fully Implantable Biosensing Applications
that enable long-term implantation can facilitate treatments for a variety of diseases and conditions [1,2]. This type of sensor system can also build off the standards used in near-field communications, which provide a
ISSCC 2013
Session 16
Medical & Bio
An Integrated Magnetic Spectrometer for Multiplexed Biosensing
There is high demand for at-home and point-of-care medical diagnostic tools as a step toward fast, low-cost, personal medicine. Integrated biosensors based on magnetic labeling schemes offer higher sensitivity and lower
ISSCC 2013
Session 16
Medical & Bio
A 20μW Intra-Cardiac Signal-Processing IC with 82dB Bio-Impedance Measurement Dynamic Range and Analog Feature Extraction for Ventricular Fibrillation Detection
of multiple intra-cardiac signals is becoming more and more important for Cardiac Resynchronization Therapy (CRT) and for the analysis of the intra-thoracic fluid status [1, 2]. Robust and accurate Heart-Rate (HR) monito
ISSCC 2013
Session 17
Memory
A 6.4Gb/s Near-Ground Single-Ended Transceiver for Dual-Rank DIMM Memory Interface Systems
Bill Stonecypher2, Wayne Dettloff2, Teva Stone2, Kashinath Prabhu3, Pravin Kumar Venkatesan3, Fred Heaton2, Ravi Kollipara1, Yi Lu1, Chris J. Madden1, John Eble2, Lei Luo2, Nhat Nguyen1 Rambus, Sunnyvale, CA, 2Rambus, Ch
ISSCC 2013
Session 17
Memory
A 27% Reduction in Transceiver Power for Single-Ended Point-to-Point DRAM Interface with the Termination Resistance of 4×Z0 at both TX and RX This integrator helps to reduce power and increase the robustness to highfrequency noise [1, 4-5].
in the single-ended point-to-point DRAM interface by increasing the termination resistance to 4×Z0 at both ends of TX and RX. The resultant increase of ISI and reflection is compensated for at RX by using the 1-tap and 2
ISSCC 2013
Session 17
Memory
A 5.7mW/Gb/s 24-to-240Ω 1.6Gb/s Thin-Oxide DDR Transmitter with 1.9-to-7.6V/ns Clock-Feathering Slew-Rate Control in 22nm CMOS impedance levels are controlled by the enable vectors (en_ffe_n/p[3:0] for FFE slices and en_n/p[7:0] for non-FFE slices). Typical impedance ranges are 24 to 40Ω in drive mode and 60 to 240Ω in ODT mode.
Matthias Brändli, Peter Buchmann, Lukas Kull, Toke Meyer Andersen, Thomas Morf To save power in the predriver, the SST stages consist of thin-oxide devices, which require overvoltage protection implemented by transistors
ISSCC 2013
Session 17
Memory
An Adaptive-Bandwidth PLL for Avoiding Noise Interference and DFE-Less Fast Precharge Sampling for over 10Gb/s/pin Graphics DRAM Interface
GDDR interface [1,4]. As the bit rate increases, jitter of PLL, data-sampling margin, crosstalk and intersymbol interference (ISI) needs considerable management [1,3,5]. Moreover, as the supply voltage decreases, the sel
ISSCC 2013
Session 18
Memory
A 20nm 112Mb SRAM in High-κ Metal-Gate with Assist Circuitry for Low-Leakage and Low-VMIN Applications
Hung-Jen Liao, Quincy Li, Stanley Chang, Sreedhar Natarajan, Robin Lee, Ping-Wei Wang, Shyue-Shyh Lin, Chung-Cheng Wu, Kuan-Lun Cheng, Min Cao, George H. Chang TSMC, Hsinchu, Taiwan A 20nm high-κ metal-gate planar CMOS t
ISSCC 2013
Session 18
Memory
An SRAM Using Output Prediction to Reduce BL-Switching Activity and Statistically-Gated SA for up to 1.9× Reduction in Energy/Access
Mobile applications such as tablets pack increasingly more processing capability comparable to workstations or laptops but can do little for cooling or extending the battery life in their form factors. SRAMs account for
ISSCC 2013
Session 18
Memory
A 27% Active and 85% Standby Power Reduction in Dual-Power-Supply SRAM Using BL Power Calculator and Digitally Controllable Retention Circuit
Miyako Shizuno, Atsushi Kawasumi, Keiichi Kushida, Azuma Suzuki, Yusuke Niki, Shinichi Sasaki, Tomoaki Yabe, Yasuo Unekawa Toshiba, Kawasaki, Japan This paper presents a dual-power-supply SRAM that reduces active and sta
ISSCC 2013
Session 18
Memory
A 64Mb SRAM in 22nm SOI Technology Featuring Fine-Granularity Power Gating and Low-Energy Power-Supply-Partition Techniques for 37% Leakage Reduction
Steven M. Lamphier1, Michael M. Lee1, Frank M. Pavlik1, Sushma N. Sambatur3, Adnan Seferagic1, Richard Wu1, Mohammad I. Younus4 IBM, Essex Junction, VT, 2IBM, Rochester, MN, 3IBM, Bangalore, India, IBM, Hopewell Junction
ISSCC 2013
Session 18
Memory
7GHz L1 Cache SRAMs for the 32nm zEnterpriseTM EC12 Processor
Uma Srinivasan1, Daniel Rodko1, Pradip Patel1, Thomas J. Knips1, Tobias Werner2 IBM, Poughkeepsie, NY, 2IBM, Boeblingen, Germany 1 The L1 cache for the 5.5 GHz 32nm zEnterpriseTM EC12 processor requires SRAM designs that
ISSCC 2013
Session 19
Wireless
A Fully Integrated 2×2 b/g and 1×2 a-Band MIMO WLAN SoC in 45nm CMOS for Multi-Radio IC
Debapriya Sahu1, Apu Sivadas1, Murali Nandigam1, Saravana Ganeshan1, Srihari Datla1, Anand Kudari1, Hemant Bhasin1, Meghna Agrawal1, Subramanian Narayan1, Yogesh Dharwekar1, Robin Garg1, Vimal Edayath1, Thirunaavukkarass
ISSCC 2013
Session 19
Wireless
A Digitally Modulated 2.4GHz WLAN Transmitter with Integrated Phase Path and Dynamic Load Modulation in 65nm CMOS
Wi-Fi transmitters (TXs) has been continuously rising, and has hence become increasingly problematic for mobile devices. To extend battery life, the TX must be efficient not only at peak power but also at backoff, due to
ISSCC 2013
Session 19
Wireless
A 24.7dBm All-Digital RF Transmitter for Multimode Broadband Applications in 40nm CMOS
Berkeley, CA 1 to the load, and AM-AM/AM-PM distortion, similar to conventional power amplifiers. Particularly in our quadrature DPA architecture, the RF current is the combined output of I-PA and Q-PA, and the effect of
ISSCC 2013
Session 19
Wireless
A Universal GNSS (GPS/Galileo/Glonass/Beidou) SoC with a 0.25mm2 Radio in 40nm CMOS
(GNSS) have a spectrum allocation shown in Fig. 19.4.1. The time-to-first-lock and location accuracy can be improved through simultaneous reception of two different satellite signals. This usually necessitates the use of
ISSCC 2013
Session 19
Wireless
A Receiver for LTE Rel-11 and Beyond Supporting Non-Contiguous Carrier Aggregation
Jim Svensson, Fenghao Mu, Thomas Olsson, Imad ud Din, Leif Wilhelmsson, Daniel Eckerbert, Sven Mattisson Ericsson, Lund, Sweden Carrier aggregation (CA) is introduced in 3GPP LTE Rel-10 [1] to meet the demand for further
ISSCC 2013
Session 19
Wireless
A Multiband 40nm CMOS LTE SAW-Less Modulator with -60dBc C-IM3
scarceness of free spectrum, the complexity and versatility of 4th-generation modulation schemes is greater than ever. In particular, the LTE standard defines multiple RF bands and groups OFDM modulated subcarriers into
ISSCC 2013
Session 19
Wireless
An LTE Transmitter Using a Class-A/B Power Mixer
Daniele Ottini1, Yong He4, Alberto Pirola1, Enrico Sacchi1, Gregory Uehara5, Chao Yang5,6, Rinaldo Castello2 Marvell, Pavia, Italy, University of Pavia, Pavia, Italy, 3 *Now at the University of Toronto, Toronto, ON, Can
ISSCC 2013
Session 19
Wireless
A 0.27mm2 13.5dBm 2.4GHz All-Digital Polar Transmitter Using 34%-Efficiency Class-D DPA in 40nm CMOS
Lanchou Cho1, Meng-Hsiung Hung1, Xin-Yu Shih1, Che-Min Lin1, Sheng-Hong Yan1, Yuan-Hung Chung1, Paul C.P. Liang1, Guang-Kaai Dehng1, Hung-Sung Li1, George Chien2, Robert Bogdan Staszewski3 MediaTek, Hsinchu, Taiwan, 2Med
ISSCC 2013
Session 2
Wireline I/O
A 32Gb/s Wireline Receiver with a Low-Frequency
Samir Parikh1, Tony Kao1, Yasuo Hidaka1, Jian Jiang1, Asako Toda1, Scott Mcleod1, William Walker1, Yochi Koyanagi2, Toshiyuki Shibuya2, Jun Yamada3 Fujitsu Laboratories of America, Sunnyvale, CA, Fujitsu Laboratories, Ka
ISSCC 2013
Session 2
Wireline I/O
A 66Gb/s 46mW 3-Tap Decision-Feedback Equalizer in 65nm CMOS
Given the continuously climbing data rates of high-speed I/O’s, equalizer circuits—and particularly decision-feedback equalizer (DFE) designs—are being pushed to operate at ever-higher speeds. At 20 to 40Gb/s data-rates,
ISSCC 2013
Session 2
Wireline I/O
A Sub-2W 39.8-to-44.6Gb/s Transmitter and Receiver Chipset with SFI-5.2 Interface in 40nm CMOS
can alleviate bandwidth bottlenecks of Internet infrastructure while simultaneously reducing operating costs. Increasingly, standard CMOS technology is used to enable transceiver speeds [1-5] previously achievable only b
ISSCC 2013
Session 2
Wireline I/O
A 195mW / 55mW Dual-Path Receiver AFE for Multistandard 8.5-to-11.5 Gb/s Serial Links in 40nm CMOS
the deployment of 10Gb/s traffic over legacy data links, such as backplanes (KR) and multimode fiber (MMF) [1]. Under severe channel impairments, an ADC-based receiver with a DSP backend provides robust performance, espe
ISSCC 2013
Session 2
Wireline I/O
32Gb/s Data-Interpolator Receiver with 2-Tap DFE in 28nm CMOS
Win Chaivipas1, Takushi Hashida1, Hiroki Miyaoka2, Masanori Hoshino3, Yoichi Koyanagi1, Takuji Yamamoto4, Sanroku Tsukamoto1, Hirotaka Tamura1 Fujitsu Laboratories, Kawasaki, Japan, Fujitsu Semiconductor, Yokohama, Japan
ISSCC 2013
Session 2
Wireline I/O
A 32-to-48Gb/s Serializing Transmitter Using Multiphase Sampling in 65nm CMOS
Serial-link transmitters are widely used in applications like optical transceivers and multi-gigabit Ethernet. At tens of Gb/s, the operating range of bit-rates is narrow; limited by the speed of the multiplexing and the
ISSCC 2013
Session 2
Wireline I/O
32Gb/s 28nm CMOS Time-Interleaved Transmitter Compatible with NRZ Receiver with DFE
Fujitsu, Kawasaki, Japan, 4 Fujitsu Microelectronics Solutions, Akiruno, Japan Since the transmitter uses 4-way interleaved quarter-rate clocking to generate the output signal, the output signal integrity is prone to dut
ISSCC 2013
Session 2
Wireline I/O
A 0.94mW/Gb/s 22Gb/s 2-Tap Partial-Response DFE Receiver in 40nm LP CMOS
A decision-feedback equalizer (DFE) reconstructs the post-cursor inter-symbol interference (ISI) pattern from the detected data sequence and subtracts it from the received signal before detecting the next symbol. Therefo
ISSCC 2013
Session 20
Clocking & PLLs
A 2.5-to-3.3GHz CMOS Class-D VCO
Power consumption in LC oscillators for wireless communications is a popular research topic, where the Class-C oscillator [1] has been proposed to improve the efficiency of the standard Class-B oscillator (most often ref
ISSCC 2013
Session 20
Clocking & PLLs
Third-Harmonic Injection Technique Applied to a 5.87-to-7.56GHz 65nm CMOS Class-F Oscillator with 192dBc/Hz FOM
Aktieve Rangschikkings Monolitische Microgolf Onderdelen B.V., Delft, The Netherlands 1 resonance frequency fosc2 to ‘snap’ to it if both are within the locking range [5]. The locking range is wide enough (±5%) due to th
ISSCC 2013
Session 20
Clocking & PLLs
A 33.6-to-46.2GHz 32nm CMOS VCO with 177.5dBc/Hz Minimum Noise FOM Using Inductor Splitting for Tuning Extension
Signal processing in ultra-wide bandwidths is one of the key challenges in the design of multi-Gb/s wireless transceivers at mm-Waves, where channels covering 57GHz to 66GHz are specified. Further considering spreads due
ISSCC 2013
Session 20
Clocking & PLLs
A 56.4-to-63.4GHz Spurious-Free All-Digital Fractional-N PLL in 65nm CMOS
University of Science and Technology of China, Hefei, China 1 2 Frequency synthesis at mm-Waves is still dominated by analog PLLs, although all-digital PLLs (ADPLLs) [1] have been widely explored below 10GHz. The major o
ISSCC 2013
Session 20
Clocking & PLLs
A 57.9-to-68.3GHz 24.6mW Frequency Synthesizer with In-Phase Injection-Coupled QVCO in 65nm CMOS
systems such as 60GHz band applications, the requirements of PLLs keep getting higher. In a mm-Wave direct-conversion transceiver, the quadrature LO signal generation is challenging. The conventional techniques to genera
ISSCC 2013
Session 20
Clocking & PLLs
A 2.4psrms-jitter Digital PLL with Multi-Output BangBang Phase Detector and Phase-Interpolator-Based Fractional-N Divider
time-to-digital converter(TDC)-based architectures [1] to avoid significant complexity and power overhead due to such a critical building block [2-4]. Architectures based on bang-bang phase detectors are very attractive
ISSCC 2013
Session 20
Clocking & PLLs
A 50-to-930MHz Quadrature-Output Fractional-N Frequency Synthesizer with 770-to-1860MHz SingleInductor LC-VCO and Without Noise Folding Effect for Multistandard DTV Tuners
Ratio Microelectronics, Shanghai, China 1 2 There are many Digital TV (DTV) standards around the world, such as DVB-T/C/H in Europe, ATSC-C/M/H in North America, TDMB in China, ISDB-T in Japan and DMB-T in South Korea. I
ISSCC 2013
Session 21
Power Management
An 82.4% Efficiency Package-Bondwire-Based Four-Phase Fully Integrated Buck Converter with Flying Capacitor for Area Reduction
Multi-phase converters have become a topic of great interest due to the high output power capacity and output ripple cancellation effect. They are even more beneficial to nowadays high-frequency fully integrated converte
ISSCC 2013
Session 21
Power Management
An AC-Coupled Hybrid Envelope Modulator for HSUPA Transmitters with 80% Modulator Efficiency
because of the fundamental correlation between data rate and transmit power. Furthermore, the high peak-to-average power ratio (PAPR) of the modulated signals causes a degradation in PA efficiency, since the supply volta
ISSCC 2013
Session 21
Power Management
A CMOS Dual-Switching Power-Supply Modulator with 8% Efficiency Improvement for 20MHz LTE Envelope Tracking RF Power Amplifiers
2 University of California, San Diego, La Jolla, CA, Brown University, Providence, RI 1 2 Envelope Tracking (ET) is an efficiency enhancement technique where the power supply of a linear RF power amplifier (PA) follows t
ISSCC 2013
Session 21
Power Management
% Efficient 11MHz 22W LED Driver Using GaN FETs and Burst-Mode Controller with 0.96 Power Factor
LEDs, the lighting industry is expected to see a significant growth in the near future. However, for LEDs to completely replace the traditional incandescent and CFL bulbs, the power converters within the LED drivers need
ISSCC 2013
Session 21
Power Management
A Fully Integrated Successive-Approximation Switched-Capacitor DC-DC Converter with 31mV Output Voltage Resolution
University of Michigan, Ann Arbor, MI Ultra-low power microsystems are gaining more popularity due to their applicability in critical areas of societal need. Power management in these microsystems is a major challenge as
ISSCC 2013
Session 21
Power Management
A Sub-ns Response Fully Integrated BatteryConnected Switched-Capacitor Voltage Regulator Delivering 0.19W/mm2 at 73% Efficiency
Lithium-ion batteries are the dominant power source in mobile devices. However, while the supply voltage required for processors and SoCs has scaled down to ~1V, the voltage range of this popular battery remains ~2.9V-4.