ISSCC 2014

2014

203 篇论文 · Digital Processors (19) · Wireless (19) · Data Converters (17) · Wireline I/O (17)

ISSCC 2014 Session 16 Digital Processors
A 23Mb/s 23pJ/b Fully Synthesized True-RandomNumber Generator in 28nm and 65nm CMOS
Kaiyuan Yang, David Fick, Michael B. Henry, Yoonmyung Lee,
David Blaauw, Dennis Sylvester locking the oscillation and impacting collapse event time. To measure noise amplitude on-chip, an asynchronous clock samples the supply voltage, compares it with an external reference volta
ISSCC 2014 Session 17 Analog Circuits
An Integrated 80V 45W Class-D Power Amplifier with Optimal-Efficiency-Tracking Switching Frequency Regulation
Haifeng Ma, Ronan van der Zee, Bram Nauta
Piezoelectric actuators are widely used in smart materials for vibration and noise control, precision actuators, etc. [1]. These actuators are largely capacitive and the reactive power applied on them can go to several t
University of Twente, Enschede, The Netherlands
ISSCC 2014 Session 17 Analog Circuits
V-Input-Voltage 0.6V-Output-Voltage 30ppm/°C Low-Dropout Regulator with Embedded Voltage Reference for Low-Power Biomedical Systems
Wei-Chung Chen, Yi-Ping Su, Yu-Huei Lee,
6V to biomedical systems requires a low dropout (LDO) regulator with a maximum driving current capability of 10mA. One sub-1V voltage reference circuit is commonly used in the conventional LDO design to generate the refe
Chin-Long Wey, Ke-Horng Chen National Chiao Tung University, Hsinchu,
ISSCC 2014 Session 17 Analog Circuits
A 0.65ns-Response-Time 3.01ps FOM Fully-Integrated Low-Dropout Regulator with Full-Spectrum Power-SupplyRejection for Wideband Communication Systems
Yan Lu, Wing-Hung Ki, C. Patrick Yue
High performance low-dropout regulators (LDOs) are indispensable in a systemon-a-chip (SoC) due to their low output noise, fast transient response and good power supply rejection (PSR) characteristics. In general, differ
Hong Kong University of Science and Technology, Hong Kong, China
ISSCC 2014 Session 17 Analog Circuits
A 0.0013mm2 3.6μW Nested-Current-Mirror SingleStage Amplifier Driving 0.15-to-15nF Capacitive Loads with >62° Phase Margin
Zushu Yan1, Pui-In Mak1,2, Man-Kay Law1,2,
Italy 1 2 For active-matrix LCDs [1] that have thousands of buffer amplifiers integrated in its column-driver ICs, ultra-low power and area circuit solutions are continuously urged to meet the market pressure on cost, im
Rui Martins1,2,3, Franco Maloberti4 University of Macau, Macao, China,
ISSCC 2014 Session 17 Analog Circuits
A 0.9V 6.3μW Multistage Amplifier Driving 500pF Capacitive Load with 1.34MHz GBW
Wanyuan Qu1, Jong-Pil Im2, Hyun-Sik Kim1, Gyu-Hyeong Cho1, 1
of driving a large capacitive load with wide bandwidth are becoming more important for various applications. The conventional frequency compensation methods, however, are based on cumbersome transfer function derivations
KAIST, Daejeon, Korea, 2ETRI, Daejeon, Korea As process scales down, l
ISSCC 2014 Session 17 Analog Circuits
CMOS Impedance Analyzer for Nanosamples Investigation Operating up to 150MHz with Sub-aF Resolution
Giorgio Ferrari, Davide Bianchi, Angelo Rottigni, Marco Sampietro
Impedance analyzers find an important role in nanoscience and in biological research as a tool to access electrical and physical parameters of the matter as well as to enhance the read-out performance in sensor applicati
Politecnico di Milano, Milan, Italy
ISSCC 2014 Session 17 Analog Circuits
A 0.07mm2 2-Channel Instrumentation Amplifier with 0.1% Gain Matching in 0.16μm CMOS
Fabio Sebastiano1,2, Federico Butti3, Robert van Veldhoven1, Paolo Bruschi3
are required for cost-constrained automotive applications. Instrumentation amplifiers (IA) for such front-ends must process multi-channel sensor outputs and provide gain matching over the channels for proper sensor opera
NXP Semiconductors, Eindhoven, The Netherlands, Delft University of Te
ISSCC 2014 Session 17 Analog Circuits
Envelope Modulator for Multimode Transmitters with AC-Coupled Multilevel Regulators
Patrik Arnò1, Matthieu Thomas2,3, Vladimír Molata2,3, Tomáš Jeřábek2
STMicroelectronics, Prague, Czech Republic, 3 Czech Technical University, Prague, Czech Republic 1 2 Modern wireless communication systems, such as high-speed uplink packet access (HSUPA) or long term evolution (LTE), em
STMicroelectronics, Grenoble, France,
ISSCC 2014 Session 17 Analog Circuits
A 1.89nW/0.15V Self-Charged XO for Real-Time Clock Generation Keng-Jan Hsiao
MediaTek, Hsinchu, Taiwan, A 32.768kHz crystal (XTAL) with its oscillation circuit is widely adopted for the
generation of the real-time keeping and system-standby clock. Both functions are universally demanded by various systems such as cellular phones, smart wearable devices, GPS, etc. High frequency stability against environ
ISSCC 2014 Session 17 Analog Circuits
A 190nW 33kHz RC Oscillator with ±0.21% Temperature Stability and 4ppm Long-Term Stability
Danielle Griffith1, Per Torstein Røine2, James Murdock1, Ryan Smith1
In wireless networks with a low duty cycle, the radio is operational for only a small percentage of the time. A sleep timer is used to synchronize the data transmission and reception. The total system power is then limit
Texas Instruments, Dallas, TX, 2Texas Instruments, Oslo, Norway
ISSCC 2014 Session 17 Analog Circuits
A 0.6V 70MHz 4th-Order Continuous-Time Butterworth
Filter with 55.8dB SNR, 60dB THD at +2.8dBm Output, Signal Power
Jayanth N. Kuppambatti, Baradwaj Vigraham, Peter R. Kinget Columbia University, New York, NY Technology scaling is leading to supply voltage reduction and shrinking voltage headroom, making it very challenging for analog
ISSCC 2014 Session 18 Medical & Bio
A 1V 3mA 2.4GHz Wireless Digital Audio Communication SoC for Hearing-Aid Applications in 0.18μm CMOS
Amre El-Hoiydi1, François Callias1, Yves Oesch1,
Hearing aids are complex integrated and highly miniaturised systems based on digital signal processor and wireless communication chips. There is a growing need for wireless connectivity between hearing aids and external
Christoph Kuratli2, Robert Kvacek3 Phonak Communications, Murten, Swit
ISSCC 2014 Session 18 Medical & Bio
A Fully-Implantable Cochlear Implant SoC with Piezoelectric Middle-Ear Sensor and Energy-Efficient Stimulation in 0.18µm HVCMOS
Marcus Yip1, Rui Jin1, Hideko Heidi Nakajima2,3,
Konstantina M. Stankovic2,3, Anantha P. Chandrakasan1 Massachusetts Institute of Technology, Cambridge, MA, Harvard Medical School, Boston, MA, 3 Massachusetts Eye and Ear Infirmary, Boston, MA 1 2 A cochlear implant (CI
ISSCC 2014 Session 18 Medical & Bio
A Multi-Parameter Signal-Acquisition SoC for Connected Personal Health Applications DC-offset isn’t cancelled after the input differential pair of the gm-stage the proposed method doesn’t face the power vs. noise vs. DC-offset range trade-off from CFBIAs with DC-servos.
Nick Van Helleputte1, Mario Konijnenburg2, Hyejung Kim1, Julia Pettine2,
Dong-Woo Jee1, Arjan Breeschoten2, Alonso Morgado1, Tom Torfs1, Harmke de Groot2, Chris Van Hoof1, Refet Firat Yazicioglu1 Various very low power signal processors have been demonstrated [2]. This is usually achieved thr
ISSCC 2014 Session 18 Medical & Bio
A 4.9mΩ-Sensitivity Mobile Electrical Impedance Tomography IC for Early Breast-Cancer Detection System
Sunjoo Hong, Kwonjoon Lee, Unsoo Ha, Hyunki Kim,
S. women will develop breast cancer over the course of her lifetime, and breast cancer death rates are higher than those for any other cancer, besides lung cancer. In 2013, an estimated 232,340 new cases of invasive brea
Yongsu Lee, Youchang Kim, Hoi-Jun Yoo KAIST, Daejeon, Korea Approximat
ISSCC 2014 Session 18 Medical & Bio
A 2.14mW EEG Neuro-Feedback Processor with Transcranial Electrical Stimulation for Mental-Health Management
Taehwan Roh, Kiseok Song, Hyunwoo Cho, Dongjoo Shin,
therapy based on Quantitative EEG (QEEG) and Event Related Potential (ERP) online data measurements. The U.S. Food and Drug Administration (FDA) approved the first EEG test for diagnosing attention deficit hyperactivity
Unsoo Ha, Kwonjoon Lee, Hoi-Jun Yoo KAIST, Daejeon, Korea Recently, me
ISSCC 2014 Session 18 Medical & Bio
D Heterogeneously Integrated Bio-Sensing Microsystem for Multi-Channel Neural-Sensing Applications
Po-Tsang Huang1, Lei-Chun Chou1, Teng-Chieh Huang1, Shang-Lin Wu1,
Tang-Shuan Wang1, Yu-Rou Lin1, Chuan-An Cheng1, Wen-Wei Shen1, Kuan-Neng Chen1, Jin-Chern Chiou1,2, Ching-Te Chuang1, Wei Hwang1, Kuo-Hua Chen3, Chi-Tsung Chiu3, Ming-Hsiang Cheng3, Yueh-Lung Lin3, Ho-Ming Tong3 National
ISSCC 2014 Session 18 Medical & Bio
A Remotely Controlled Locomotive IC Driven by Electrolytic Bubbles and Wireless Powering
Po-Hung Kuo1, Jian-Yu Hsieh1, Yi-Chun Huang1, Yu-Jie Huang1,
Taoyuan, Taiwan 1 As implantable medical CMOS devices become a reality [1], motion control of such implantable devices has become the next challenge in the advanced integrated micro-system domain. With integrated sensors
Rong-Da Tsai2, Tao Wang3, Hung-Wei Chiu2, Shey-Shi Lu1 National Taiwan
ISSCC 2014 Session 19 Memory
A 128Gb MLC NAND-Flash Device Using 16nm Planar Cell
Mark Helm1, Jae-Kwan Park1, Ali Ghalam1, Jason Guo1, Chang wan Ha1,
Cairong Hu1, Heonwook Kim1, Kalyan Kavalipurapu1, Eric Lee1, Ali Mohammadzadeh1, Dan Nguyen1, Vipul Patel1, Ted Pekny1, Bill Saiki1, Daesik Song1, Jeff Tsai1, Vimon Viajedor1, Luyen Vu1, Tinwai Wong1, Jung Hee Yun1, Rami
ISSCC 2014 Session 19 Memory
A 93.4mm2 64Gb MLC NAND-Flash Memory with 16nm CMOS Technology
Sungdae Choi, Duckju Kim, Sungwook Choi, Byungryul Kim,
Sunghyun Jung, Kichang Chun, Namkyeong Kim, Wanseob Lee, Taisik Shin, Hyunjong Jin, Hyunchul Cho, Sunghoon Ahn, Yonghwan Hong, Ingon Yang, Byoungyoung Kim, Pilseon Yoo, Youngdon Jung, Jinwoo Lee, Jaehyeon Shin, Taeyun Ki
ISSCC 2014 Session 19 Memory
KIOPS-Random-Read 690MB/s-Sequential-Read Universal Flash Storage Device Controller with Unified Memory Extension
Konosuke Watanabe1, Kenichiro Yoshii1, Nobuhiro Kondo1,
Kenichi Maeda1, Toshio Fujisawa1, Junji Wadatsumi2, Daisuke Miyashita2, Shouhei Kousai2, Yasuo Unekawa2, Shinsuke Fujii2, Takuma Aoyama2, Takayuki Tamura1, Atsushi Kunimatsu1, Yukihito Oowaki1 Toshiba, Yokohama, Japan, 2
ISSCC 2014 Session 19 Memory
Embedded 1Mb ReRAM in 28nm CMOS with 0.27-to1V Read Using Swing-Sample-and-Couple Sense Amplifier and Self-Boost-Write-Termination Scheme
Meng-Fan Chang1, Jui-Jen Wu1, Tun-Fei Chien1, Yen-Chen Liu1,
Ting-Chin Yang1, Wen-Chao Shen1, Ya-Chin King1, Chorng-Jung Lin1, Ku-Feng Lin2, Yu-Der Chih2, Sreedhar Natarajan2, Jonathan Chang2 National Tsing Hua University, Hsinchu, Taiwan, 2TSMC, Hsinchu, Taiwan 1 Resistive RAM (R
ISSCC 2014 Session 19 Memory
Three-Dimensional 128Gb MLC Vertical NAND FlashMemory with 24-WL Stacked Layers and 50MB/s High-Speed Programming are reprogrammed in the next program pulse. As a result, the wider programmed
Vth distribution due to fast detrapping is reduced. Additionally, by incorporating, the cell characteristics mentioned a
with performance of 50MB/s write throughput. Ki-Tae Park, Jin-man Han, Daehan Kim, Sangwan Nam, Kihwan Choi, Min-Su Kim, Pansuk Kwak, Doosub Lee, Yoon-He Choi, Kyung-Min Kang, Myung-Hoon Choi, Dong-Hun Kwak, Hyun-wook Pa
ISSCC 2014 Session 19 Memory
Hybrid Storage of ReRAM/TLC NAND Flash with RAID-5/6 for Cloud Data Centers
Shuhei Tanakamaru1,2, Hiroki Yamazawa1, Tsukasa Tokutomi1,
RAID-5/6 is developed to meet cloud data-center requirements of reliability, speed and capacity. The storage controller enhances reliability and performance through five techniques with minimal area overhead. The first t
Sheyang Ning1,2, Ken Takeuchi1 Chuo University, Tokyo, Japan, 2Univers
ISSCC 2014 Session 19 Memory
A 16Gb ReRAM with 200MB/s Write and 1GB/s Read in 27nm Technology
Richard Fackenthal1, Makoto Kitagawa2, Wataru Otsuka2, Kirk Prall3,
Duane Mills1, Keiichi Tsutsui4, Jahanshir Javanifard1, Kerry Tedrow1, Tomohito Tsushima2, Yoshiyuki Shibahara4, Glen Hush3 Micron, Folsom, CA, Sony, Boise, ID, 3 Micron, Boise, ID, 4 Sony, Kanagawa, Japan 1 2 Resistive R
ISSCC 2014 Session 2 Wireline I/O
28Gb/s 560mW Multi-Standard SerDes with SingleStage Analog Front-End and 14-Tap DecisionFeedback Equalizer in 28nm CMOS
Hiroshi Kimura, Pervez Aziz, Tai Jing, Ashutosh Sinha, Ram Narayan,
Hairong Gao, Ping Jing, Gary Hom, Anshi Liang, Eric Zhang, Aniket Kadkol, Ruchi Kothari, Gordon Chan, Yehui Sun, Benjamin Ge, Jason Zeng, Kathy Ling, Michael Wang, Amaresh Malipatil, Shiva Kotagiri, Lijun Li, Chris Abel,
ISSCC 2014 Session 2 Wireline I/O
A 780mW 4×28Gb/s Transceiver for 100GbE Gearbox PHY in 40nm CMOS
Ullas Singh, Adesh Garg, Bharath Raghavan, Nick Huang,
centers and network operators to support data-rich services like video streaming and social media. This has accelerated the adoption of 100Gb/s connectivity from the present 10Gb/s and 40Gb/s rates. One challenge that re
Heng Zhang, Zhi Huang, Afshin Momtaz, Jun Cao Broadcom, Irvine, CA Net
ISSCC 2014 Session 2 Wireline I/O
60Gb/s NRZ and PAM4 Transmitters for 400GbE in 65nm CMOS
Ping-Chuan Chiang1,2, Hao-Wei Hung1, Hsiang-Yun Chu1,
40Gb/s are practical to implement in CMOS technology [1]. However, next-generation datacom and telecom systems require transceivers to operate at even higher data rates. For example, a 400Gb/s Ethernet system may need 8×
Guan-Sing Chen1, Jri Lee1,2 National Taiwan University, Taipei, Taiwan
ISSCC 2014 Session 2 Wireline I/O
A 25Gb/s 5.8mW CMOS Equalizer
Jun Won Jung, Behzad Razavi
The power consumption of broadband receivers becomes particularly critical in multi-lane applications such as the 100 Gigabit Ethernet. However, the powerspeed trade-off tends to intensify at higher rates, making it a gr
University of California, Los Angeles, CA
ISSCC 2014 Session 2 Wireline I/O
A 0.25pJ/b 0.7V 16Gb/s 3-Tap Decision-Feedback Equalizer in 65nm CMOS
Rui Bai1, Samuel Palermo2, Patrick Yin Chiang1,3
Texas A&M University, College Station, TX, 3 Fudan University, Shanghai, China 1 2 Supply-voltage scaling has become one of the most effective methods to improve the energy efficiency of power-constrained systems, motiva
Oregon State University, Corvallis, OR,
ISSCC 2014 Session 2 Wireline I/O
A 5.67mW 9Gb/s DLL-Based Reference-less CDR with Pattern-Dependent Clock-Embedded Signaling for Intra-Panel Interface
Dong Hoon Baek1,2, Byungsub Kim1, Hong-June Park1, Jae-Yoon Sim1
Samsung Electronics, Yongin, Korea 1 2 Point-to-point data transmission with clock-embedded signaling (CES) has been generally adopted in intra-panel interfaces, which need to support fine resolution, high frame rate, an
Pohang University of Science and Technology, Pohang, Korea,
ISSCC 2014 Session 2 Wireline I/O
A Coefficient-Error-Robust FFE TX with 230% EyeVariation Improvement Without Calibration in 65nm CMOS Technology
Seungho Han, Sooeun Lee, Minsoo Choi, Jae-Yoon Sim,
(FFE) transmitter (TX) for massively parallel links. Recently, massively parallel links such as on-chip links [1-3], silicon interposers [4,5], or wide I/Os [6] are gaining popularity to meet increasing demand for data t
Hong-June Park, Byungsub Kim Pohang University of Science and Technolo
ISSCC 2014 Session 2 Wireline I/O
A Pulse-Position-Modulation Phase-Noise-Reduction Technique for a 2-to-16GHz Injection-Locked Ring Oscillator in 20nm CMOS
Jun-Chau Chien1, Parag Upadhyaya2, Howard Jung2, Stanley Chen2,
Wayne Fang2, Ali M. Niknejad1, Jafar Savoj2, Ken Chang2 University of California, Berkeley, CA, Xilinx, San Jose, CA 1 2 High-speed transceivers embedded inside FPGAs require softwareprogrammable clocking circuits to cov
ISSCC 2014 Session 2 Wireline I/O
A Background Calibration Technique to Control Bandwidth in Digital PLLs
Giovanni Marzin, Salvatore Levantino, Carlo Samori, Andrea L. Lacaita
parameters that are subject to process, temperature and voltage spreads, as well as to variations along the frequency-tuning range. Even in digital PLLs, which rely on a digital loop filter, the bandwidth still depends o
Politecnico di Milano, Milan, Italy The bandwidth of a phased-locked l
ISSCC 2014 Session 20 Wireless
A 40nm CMOS Receiver for 60GHz Discrete-Carrier Indoor Localization Achieving mm-Precision at 4m Range
Tom Redant, Tuba Ayhan, Nico De Clercq, Marian Verhelst,
recently gained a lot of attention. Its broad bandwidth, combined with a high allowed transmitted power level, provides an excellent opportunity for numerous applications, among others high-precision ranging and localiza
Patrick Reynaert, Wim Dehaene KU Leuven, Leuven, Belgium The globally
ISSCC 2014 Session 20 Wireless
A 16TX/16RX 60GHz 802.11ad Chipset with Single Coaxial Interface and Polarization Diversity
Michael Boers1, Iason Vassiliou2, Saikat Sarkar1, Sean Nicolson1,
Ehsan Adabi1, Bagher Afshar1, Bevin Perumana1, Theodoros Chalvatzis2, Spyros Kavadias2, Padmanava Sen1, Wei Liat Chan1, Alvin Yu1, Ali Parsa3, Med Nariman1, Seunghwan Yoon1, Alfred Grau Besoli1, Chryssoula Kyriazidou2, G
ISSCC 2014 Session 20 Wireless
A 64-QAM 60GHz CMOS Transceiver with 4-Channel Bonding best TX EVM of -29.7dB is achieved in QPSK (ch.4). The PA consumes 115mW, and the two differential amplifiers and mixers consume 16mW.
Kenichi Okada, Ryo Minami, Yuuki Tsukui, Seitaro Kawai, Yuuki Seo, Shinji Sato,
Satoshi Kondo, Tomohiro Ueno, Yasuaki Takeuchi, Tatsuya Yamaguchi, Ahmed Musa, Rui Wu, Masaya Miyahara, Akira Matsuzawa The RX conversion gain is more than 20dB, excluding the PCB loss. SNDR at the center frequency of 61
ISSCC 2014 Session 20 Wireless
A Fully Integrated Single-Chip 60GHz CMOS Transceiver with Scalable Power Consumption for Proximity Wireless Communication
Shigehito Saigusa, Toshiya Mitomo, Hidenori Okuni, Masahiro Hosoya,
Akihide Sai, Shusuke Kawai, Tong Wang, Masanori Furuta, Kei Shiraishi, Koichiro Ban, Seiichiro Horikawa, Tomoya Tandai, Ryoko Matsuo, Takeshi Tomizawa, Hiroaki Hoshino, Junya Matsuno, Yukako Tsutsumi, Ryoichi Tachibana,
ISSCC 2014 Session 20 Wireless
A 40nm Dual-Band 3-Stream 802.11a/b/g/n/ac MIMO WLAN SoC with 1.1Gb/s Over-the-Air Throughput
Ming He, Renaldi Winoto, Xiang Gao, Wayne Loeb, David Signoff,
Wai Lau, Yuan Lu, Donghong Cui, Kun-Seok Lee, Sai-Wang Tam, Philip Godoy, Yung Chen, Sanghoon Joo, Changhui Hu, Arvind Anumula Paramanandam, Xiaoyue Wang, Chi-Hung Lin, Li Lin Marvell, Santa Clara, CA The steep growth of
ISSCC 2014 Session 20 Wireless
A Blocker-Resilient Wideband Receiver with Low-Noise Active Two-Point Cancellation of >0dBm TX Leakage and TX Noise in RX Band for FDD/Co-Existence
Jin Zhou, Peter R. Kinget, Harish Krishnaswamy
The demand for lower cost and form factor and increased re-configurability in wireless systems has driven the investigation of blocker-tolerant softwaredefined radios [1-4]. While promising, a reduction in system form-fa
Columbia University, New York, NY
ISSCC 2014 Session 20 Wireless
A Multi-Band Inductor-Less SAW-Less 2G/3G-TDSCDMA Cellular Receiver in 40nm CMOS
Ming-Da Tsai, Chih-Fan Liao, Chi-Yun Wang, Yi-Bin Lee, Bosen Tzeng, Guang-Kaai Dehng
evolution of cellular phone networks. New-generation cellular standards use wider channel bandwidth and more sophisticated modulation to obtain higher data-rates. Due to various cellular standards, chip providers are req
MediaTek, Hsinchu, Taiwan The growing demand for high-speed wireless c
ISSCC 2014 Session 20 Wireless
A 20mW GSM/WCDMA Receiver with RF Channel Selection
Joung Won Park, Behzad Razavi
Recent work on RF receivers has exploited N-path filters to address two critical issues, namely, blocker tolerance and high RF selectivity [1,2]. However, these designs face three drawbacks: (1) the low-noise amplifier (
University of California, Los Angeles, CA
ISSCC 2014 Session 21 Clocking & PLLs
A 1.7GHz MDLL-Based Fractional-N Frequency Synthesizer with 1.4ps RMS Integrated Jitter and 3mW Power Using a 1b TDC
Giovanni Marucci, Andrea Fenaroli, Giovanni Marzin,
Salvatore Levantino, Carlo Samori, Andrea L. Lacaita Politecnico di Milano, Milan, Italy The introduction of inductorless frequency synthesizers into standardized wireless systems still requires a high level of innovatio
ISSCC 2014 Session 21 Clocking & PLLs
A 2.3GHz Fractional-N Dividerless Phase-Locked Loop with -112dBc/Hz In-Band Phase Noise
Po-Chun Huang, Wei-Sung Chang, Tai-Cheng Lee
Recently, dividerless PLL architectures, including sub-sampling PLLs [1] and injection-locked PLLs [2], have been reported to achieve superior phase noise with respect to conventional PLL architectures. However, these di
National Taiwan University, Taipei, Taiwan
ISSCC 2014 Session 21 Clocking & PLLs
A 2GHz 130mW Direct-Digital Frequency Synthesizer with a Nonlinear DAC in 55nm CMOS
Taegeun Yoo1, Yun-Hwan Jung1, Hong Chang Yeoh1,2, Yong Sin Kim1,
employed in many frequency-agile communication systems because of their wide bandwidth, fine frequency resolution, and fast frequency-hopping characteristics. Recent developments in DDFSs are towards enhancing performanc
Sung-Mo Kang3, Kwang-Hyun Baek1 Chung-Ang University, Seoul, Korea, 2A
ISSCC 2014 Session 21 Clocking & PLLs
A 42mW 230fs-Jitter Sub-sampling 60GHz PLL in 40nm CMOS
Viki Szortyka1,2, Qixian Shi1,2, Kuba Raczkowski1, Bertrand Parvais1,
11ad standard, the LO synthesis needs both a low-noise VCO and low in-band phase noise. In the PLL shown in this paper, a QVCO with superharmonic passive coupling exhibits a large swing and low phase noise even with a 0.
Maarten Kuijk2, Piet Wambacq1,2 imec, Heverlee, Belgium, 2Vrije Univer
ISSCC 2014 Session 21 Clocking & PLLs
A 3.24-to-8.45GHz Low-Phase-Noise ModeSwitching Oscillator
Mazhareddin Taghivand1,2, Kamal Aggarwal1, Ada S. Y. Poon1
Qualcomm, San Jose, CA 1 2 VCO design for cellular applications to achieve universal coverage for a wide range of frequencies (400MHz to 3700MHz) in different standards and meeting stringent out-of-band and in-band phase
Stanford University, Stanford, CA,
ISSCC 2014 Session 21 Clocking & PLLs
A 2.4-to-5.3GHz Dual-Core CMOS VCO with Concentric 8-Shaped Coils
Luca Fanori1,2, Thomas Mattsson3, Pietro Andreani1,3
now at Marvell, Pavia, Italy, 3 Ericsson Modems, Lund, Sweden 1 2 Despite recent attempts to relax the phase-noise demands on voltage-controlled oscillators (VCOs) for cellular communications [1], mainstream radios requi
Lund University, Lund, Sweden,
ISSCC 2014 Session 21 Clocking & PLLs
A 1.8mW PLL-Free Channelized 2.4GHz ZigBee Receiver Utilizing Fixed-LO TemperatureCompensated FBAR Resonator
Keping Wang1, Jabeom Koo1, Richard Ruby2, Brian Otis1
Avago Technologies, San Jose, CA 1 feed forward the RF signal into M4 and M6 to reduce the differential signal imbalance. Simulated results show that the gain and phase imbalance of the proposed LNA are improved by 5.6dB
University of Washington, Seattle, WA,