ISSCC 2016
Session 16
Other
A Nanogap Transducer Array on 32nm CMOS for Electrochemical DNA Sequencing source follower’s drop. Thick gate devices also relax ESD constraints for the postprocessing steps required to construct the sensors.
Noureddine Tayebi1, Grace M. Credo1, David J. Liu1, Handong Li1, Kai Wu1, Xing Su1, Madoo Varma1, Oguz H. Elibol1 Architecturally each array is arranged like an imager and the chip contains 8 arrays of 32×32 pixels for a
ISSCC 2016
Session 16
Other
A Keccak-Based Wireless Authentication Tag with per-Query Key Update and Power-Glitch Attack Countermeasures
While small lowcost tagging solutions for supply-chain management exist, security in the face of fault-injection [1] and side-channel attacks [2] remains a concern. Power glitch attacks [3] in particular attempt to leak
ISSCC 2016
Session 16
Other
A 16×16 pixels SPAD-based 128-Mb/s Quantum Random Number Generator with -74dB Light Rejection Ratio and -6.7ppm/°C Bias Sensitivity on Temperature
Alessio Meneghetti2, Hesong Xu1, Daniele Perenzoni1, Guglielmo Morgari3, David Stoppa1 Fondazione Bruno Kessler, Trento, Italy, 2University of Trento, Povo, Italy, 3Telsy, Torino, Italy 1 A robust true random number gene
ISSCC 2016
Session 16
Other
A Flexible EEG Acquisition and Biomarker Extraction System Based on Thin-Film Electronics
Sigurd Wagner, James C. Sturm, Naveen Verma Princeton University, Princeton, NJ EEG is an important modality for many medical purposes. However, the lowamplitude of signals (10-to-100μV) and large number of channels (~20
ISSCC 2016
Session 16
Other
A Flexible Thin-Film Pixel Array with a Chargeto-Current Gain of 59μA/pC and 0.33% Nonlinearity and a Cost Effective Readout Circuit for Large-Area X-ray Imaging
medical-grade, high resolution, high dynamic range X-ray backplane based on a-IGZO thin-film technology with fast readout. This enables low dose, video rate X-ray imaging. Fast X-ray imaging will find its applications no
ISSCC 2016
Session 16
Other
Flexible Thin-Film NFC Transponder Chip Exhibiting Data Rates Compatible to ISO NFC Standards Using Self-Aligned Metal-Oxide TFTs
logic circuits, we have measured 19-stage ring oscillators. Figure 16.6.3 plots the measured stage delay as a function of varying supply voltage. At 0.5V VDD and 1V Vbias, the ring oscillator exhibits a frequency of 28kH
ISSCC 2016
Session 16
Other
A Fully-Integrated Half-Duplex Data/Power
isolation is becoming an essential requisite for several low-power applications, such as sensor interfaces and medical devices. In the last years, different solutions of silicon-integrated data transmission with galvanic
ISSCC 2016
Session 16
Other
A 3-to-40V 10-to-30MHz Automotive-Use GaN Driver with Active BST Balancing and VSW DualEdge Dead-Time Modulation Achieving 8.3% Efficiency Improvement and 3.4ns Constant Propagation Delay
automotive electronics has placed mounting pressure on silicon-based power converters to be increasingly reliable and efficient. Automotive electronics operate from the car battery (VIN) which experiences cold-cranks and
ISSCC 2016
Session 17
Memory
A 10nm FinFET 128Mb SRAM with Assist
Taejoong Song, Woojin Rim, Sunghyun Park, Yongho Kim, Jonghoon Jung, Giyong Yang, Sanghoon Baek, Jaeseung Choi, Bongjae Kwon, Yunwoo Lee, Sungbong Kim, Gyuhong Kim, Hyo-Sig Won, Ja-Hum Ku, Sunhom Steve Paak, ES Jung, Ste
ISSCC 2016
Session 17
Memory
Mb/mm2 1R1W 8T SRAM Arrays Operating down to 560mV Utilizing Small-Signal Sensing with Charge-Shared Bitline and Asymmetric Sense Amplifier in 14nm FinFET CMOS Technology
which use multiport memories to improve performance by enabling multiple simultaneous operations in the same memory bank. Conventional 2-read/write 8T dual-port SRAMs (2RW) suffer from read and write disturb issues when
ISSCC 2016
Session 17
Memory
A Reconfigurable Dual-Port Memory with Error Detection and Correction in 28nm FDSOI
systems-on-chip and usually limits their voltage scalability, due to the major impact of process/voltage/temperature (PVT) variations at low voltages [1]. Assist techniques to extend SRAM operating voltage range improve
ISSCC 2016
Session 18
Memory
A 20nm 9Gb/s/pin 8Gb GDDR5 DRAM with an
Hye-Yoon Joo, Seung-Jun Bae, Young-Soo Sohn, Young-Sik Kim, Kyung-Soo Ha, Min-Su Ahn, Young-Ju Kim, Yong-Jun Kim, Young-Ju Kim, Ju-Hwan Kim, Won-Jun Choi, Chang-Ho Shin, Soo Hwan Kim, Byeong-Cheol Kim, Seung-Bum Ko, Kwan
ISSCC 2016
Session 18
Memory
A 1.2V 20nm 307GB/s HBM DRAM with At-Speed Wafer-Level I/O Test Scheme and Adaptive Refresh Considering Temperature Distribution
Seong-Young Seo, Min-Sang Park, Dong-Hak Shin, Won-Chang Jung, Sang-Hoon Shin, Je-Min Ryu, Hye-Seung Yu, Jae-Hun Jung, Kyung-Woo Nam, Seouk-Kyu Choi, Jae-Wook Lee, Uksong Kang, Young-Soo Sohn, Jung-Hwan Choi, Chi-Wook Ki
ISSCC 2016
Session 18
Memory
A 1.2V 64Gb 8-Channel 256GB/s HBM DRAM with Peripheral-Base-Die Architecture and Small-Swing Technique on Heavy Load Interface
Dae Suk Kim, Chunseok Jeong, Tae Sik Yun, Hongjung Kim, Ho Sung Cho, Yeon Ok Kim, Jae Hwan Kim, Jin Ho Kim, Sangmuk Oh, Hyun Sung Lee, Ki Hun Kwon, Dong Beom Lee, Young Jae Choi, Jeajin Lee, Hyeon Gon Kim, Jun Hyun Chun,
ISSCC 2016
Session 18
Memory
An 1.1V 68.2GB/s 8Gb Wide-IO2 DRAM with Non-Contact Microbump I/O Test Scheme
Tae Yong Lee, Nohhyup Kwak, Woo Yeol Shin, Na Yeon Kim, Yunseok Hong, Kyeong Pil Kang, Dong Yoon Ka, Seong Ju Lee, Yong Sun Kim, Young Kyu Noh, Jaehoon Kim, Dong Keum Kang, Ho Uk Song, Hyeon Gon Kim, Jonghoon Oh SK hynix
ISSCC 2016
Session 19
Digital Circuits
A 0.5-to-9.5GHz 1.2µs-Lock-Time Fractional-N DPLL with ±1.25% UI Period Jitter in 16nm CMOS For Dynamic Frequency and Core-Count Scaling in SoC
incorporate power management techniques such as dynamic frequency scaling (DFS), which dynamically changes operating frequencies, and dynamic core-count scaling (DCCS), which rapidly power cycles the cores between active
ISSCC 2016
Session 19
Digital Circuits
A 0.2-to-1.45GHz Subsampling Fractional-N AllDigital MDLL with Zero-Offset Aperture PD-Based Spur Cancellation and In-Situ Timing Mismatch Detection
Multiplying delay-locked loops (MDLLs) are gaining popularity due to their superior noise performance over conventional phase-locked loops (PLLs) [1,2]. Recent designs are trending towards an all-digital implementation t
ISSCC 2016
Session 19
Digital Circuits
A 2.4GHz 1.5mW Digital MDLL Using Pulse-Width Comparator and Double Injection Technique in 28nm CMOS
low-jitter clock generator, as it does not suffer much from jitter accumulation [1-4]. By periodically replacing the output edge of the oscillator by a clean edge of the reference, an MDLL has a large effective loop band
ISSCC 2016
Session 19
Digital Circuits
A 0.17-to-3.5mW 0.15-to-5GHz SoC PLL with 15dB Built-In Supply Noise Rejection and Self-Bandwidth Control in 14nm CMOS
architectures can employ more than 20 PLLs [1]. To address SoC clocking needs with an ever reducing power budget, a deep sub-mW to low-mW PLL having a FoM between -226dB and -234dB from 0.8GHz to 5GHz is presented. The P
ISSCC 2016
Session 19
Digital Circuits
A 3.2GHz Digital Phase-Locked Loop with Background Supply-Noise Cancellation
Phase-locked loops (PLLs) are widely used in various applications such as processors, consumer electronics, and wireline communication systems. When digital circuits and a PLL with a ring oscillator are integrated togeth
ISSCC 2016
Session 19
Digital Circuits
Voltage-Scalable Frequency-Independent Quasi-Resonant Clocking Implementation of a 0.7-to-1.2V DVFS System
Clock power remains a substantial contributor to power dissipation, from ultralow-power to high-performance systems [1, 2, 3]. Recently, resonant clocking has been shown to achieve power reduction in clock distribution n
ISSCC 2016
Session 19
Digital Circuits
A 65nm CMOS ADPLL with 360μW 1.6ps-INL SS-ADC-Based Period-Detection-Free TDC
an all-digital PLL (ADPLL). In such studies, a key topic relates to the resolution and linearity of the TDC. Power-hungry techniques, such as a Vernier delay line (VDL) and a time amplifier (TA) [1,2], have been proposed
ISSCC 2016
Session 19
Digital Circuits
A 0.0021mm2 1.82mW 2.2GHz PLL Using TimeBased Integral Control in 65nm CMOS
generators in analog, digital, RF, and embedded systems to generate a high frequency output clock from a low frequency reference clock. Modern systems-on-chip (SoCs) require many such PLLs that cater to multi-core proces
ISSCC 2016
Session 2
RF & Wireless
An Integrated 0.56THz Frequency Synthesizer with 21GHz Locking Range and -74dBc/Hz Phase Noise at 1MHz Offset in 65nm CMOS
Richard Al Hadi1, Yanghyo Kim1,2, Adrian Tang1,2, Theodore Reck2, Huan-Neng Chen3, Chewnpu Jou3, Fu-Lung Hsueh3, Mau-Chung Frank Chang1,4 University of California, Los Angeles, CA, Jet Propulsion Laboratory, Pasadena, CA
ISSCC 2016
Session 2
RF & Wireless
A Scalable 28GHz Coupled-PLL in 65nm CMOS with Single-Wire Synchronization for LargeScale 5G mm-Wave Arrays
Demonstrations of mm-Wave arrays with >50 elements in silicon has led to an interest in large-scale mm-Wave MIMO arrays for 5G networks, which promise substantial improvements in network capacity [1,2]. Practical conside
ISSCC 2016
Session 2
RF & Wireless
A 4.2μs-Settling-Time 3rd-Order 2.1GHz PhaseNoise-Rejection PLL Using a Cascaded TimeAmplified Clock-Skew Sub-Sampling DLL
tuning range compared with LC-VCO-based PLLs. However, they typically have higher jitter and larger frequency drift due to high sensitivity to PVT variations. Several PLL architectures were proposed to reject the phase n
ISSCC 2016
Session 2
RF & Wireless
A 2-to-16GHz BiCMOS ΔΣ Fractional-N PLL Synthesizer with Integrated VCOs and Frequency Doubler for Wireless Backhaul Applications
STMicroelectronics, Catania, Italy The flourishing of ubiquitous wireless communication networks has pushed the development and deployment of complex RF telecom systems. Concurrently, the IC industry has been making an e
ISSCC 2016
Session 2
RF & Wireless
A Complementary VCO for IoE that Achieves a 195dBc/Hz FOM and Flicker Noise Corner of 200kHz
An LC oscillator can achieve near optimal performance if the common-mode of the circuit is designed to resonate at twice the oscillation frequency [1-3]. Common-mode resonance can be accomplished with an explicit tail in
ISSCC 2016
Session 2
RF & Wireless
A 190.5GHz Mode-Switching VCO with 20.7% Continuous Tuning Range and Maximum Power of -2.1dBm in 0.13μm BiCMOS
Wideband mm-Wave and terahertz (THz) applications, including high data-rate communications, high-resolution radar and spectroscopy, require wideband signal sources. Nevertheless, low quality factor of varactors and lossy
ISSCC 2016
Session 2
RF & Wireless
A 0.003mm2 1.7-to-3.5GHz Dual-Mode TimeInterleaved Ring-VCO Achieving 90-to-150kHz 1/f3 Phase-Noise Corner
Instituto Superior Tecnico, Lisbon, Portugal 1 3 Ring-VCOs (RVCOs) [1] have been avoided for over a decade for highperformance RF systems due to their much lower FOM (<165dB [2]) than that of their LC counterparts from l
ISSCC 2016
Session 2
RF & Wireless
A Mixed-Mode Injection Frequency-Locked Loop for Self-Calibration of Injection Locking Range and Phase Noise in 0.13μm CMOS
Virginia Tech, Blacksburg, VA Injection-locked oscillators (ILOs) are widely used to realize low-noise carrier sources, particularly at mm-Waves by leveraging harmonic injection, but only within a narrow locking range (Δ
ISSCC 2016
Session 2
RF & Wireless
A 2GHz 244fs-Resolution 1.2ps-Peak-INL EdgeInterpolator-Based Digital-to-Time Converter in 28nm CMOS
Universität München, Munich, Germany 1 4 Digital-to-time converters (DTC) generate a clock with a time delay (or phase shift) based on a digital input code. They can be used in clock-and-data-recovery (CDR) circuits [1,2
ISSCC 2016
Session 20
RF & Wireless
A 300GHz 40nm CMOS Transmitter with 32-QAM 17.5Gb/s/ch Capability over 6 Channels
Shinsuke Hara2, Akifumi Kasamatsu2, Koichi Mizuno3, Kazuaki Takahashi3, Takeshi Yoshida1, Minoru Fujishima1 Hiroshima University, Hiroshima, Japan, National Institute of Information and Communications Technology, Koganei
ISSCC 2016
Session 20
RF & Wireless
A 68.1-to-96.4GHz Variable-Gain Low-Noise Amplifier in 28nm CMOS
To allow a maximum theoretical data-rate of 25Gb/s over a 1km distance using 64QAM, an E-Band system should feature a 20dBm-output-power TX and an RX with 10dB maximum noise figure (NF) over two bands of 5GHz from 71 to
ISSCC 2016
Session 20
RF & Wireless
A Frequency-Reconfigurable mm-Wave Power Amplifier with Active-Impedance Synthesis in an Asymmetrical Non-Isolated Combiner
A frequency-agile mm-Wave power amplifier capable of reconfiguring itself to operate near-optimally over a wide range of tunable frequencies, yet producing output power >22dBm with PAE>20%, is useful for a wide range of
ISSCC 2016
Session 20
RF & Wireless
An 86-to-94.3GHz Transmitter with 15.3dBm Output Power and 9.6% Efficiency in 65nm CMOS
Southeast University, Nanjing, China to the TA high gain, the detection inaccuracy of Δt due to the circuit mismatch in PD and CP2 becomes negligibly small. VCCP is designed as a voltage-controlled current source as show
ISSCC 2016
Session 20
RF & Wireless
A 300GHz Wirelessly Locked 2×3 Array Radiating 5.4dBm with 5.1% DC-to-RF Efficiency in 65nm CMOS
CMOS technology innovations over the last decades opened doors to the possibility of designing fully integrated systems in CMOS at THz frequencies. Small antenna sizes at THz frequencies make CMOS and silicon attractive
ISSCC 2016
Session 20
RF & Wireless
A 28GHz Efficient Linear Power Amplifier for 5G Phased Arrays in 28nm Bulk CMOS
driving fifthgeneration (5G) wireless standardization towards the deployment of gigabit-per-second mm-Wave technology by 2020. Paving the road to 5G, 200m coverage in non-line-of-sight (NLOS) urban cells was demonstrated
ISSCC 2016
Session 20
RF & Wireless
An RF-PA Supply Modulator Achieving 83% Efficiency and -136dBm/Hz Noise for LTE-40MHz and GSM 35dBm Applications
constant supply voltage, has raised interest in enhancing the overall SM-PA efficiency. In the average-powertracking (APT) method, a buck converter simply generates stair-case voltages for a PA according to its required
ISSCC 2016
Session 20
RF & Wireless
A Dual-Frequency 0.7-to-1GHz Balance Network for Electrical Balance Duplexers
seeks to address several key challenges of 4G and 5G mobile systems [1]. The basic principle is shown in Fig. 20.8.1. Duplexer isolation is achieved when the signals in paths 1 and 2 cancel and prevent the TX signal from
ISSCC 2016
Session 20
RF & Wireless
A 1.92mW Filtering Transimpedance Amplifier for RF Current Passive Mixers
Nowadays, current passive mixers represent the state of the art for signal downconversion in wireless receivers. In such kind of structures, noise, distortions and losses are strictly correlated to the performance of the
ISSCC 2016
Session 21
Wireless
A Single-Cycle MPPT Charge-Pump Energy Harvester Using a Thyristor-Based VCO Without Storage Capacitor
The switched-capacitor power converter, also called a charge pump (CP), features no off-chip components and is suitable for the monolithic smart nodes in the internet of everything (IoE) [1]. To reduce the inevitable cha
ISSCC 2016
Session 21
Wireless
A 4µW-to-1mW Parallel-SSHI Rectifier for Piezoelectric Energy Harvesting of Periodic and
Improvement Daniel A. Sanchez1, Joachim Leicht1, Eduardas Jodka1, Elham Fazel1, Yiannos Manoli1,2 University of Freiburg - IMTEK, Freiburg, Germany, Hahn-Schickard, Villingen-Schwenningen, Germany 1 2 A piezoelectric ene
ISSCC 2016
Session 21
Wireless
A 200nA Single-Inductor Dual-Input-Triple-Output (DITO) Converter with Two-Stage Charging and Process-Limit Cold-Start Voltage for Photovoltaic and Thermoelectric Energy Harvesting
Analog Devices, Wilmington, MA, 3 Analog Devices, San Jose, CA 1 2 Energy harvesting has been considered to be a good solution to power many IoE applications [1-3]. Some applications require regulated supply voltage, whi
ISSCC 2016
Session 21
Wireless
A >78%-Efficient Light Harvester over 100-to100klux with Reconfigurable PV-Cell Network and MPPT Circuit
extend system lifetime for internet of everything (IoE) nodes. Ambient light is a common energy source that can be harvested by photovoltaic (PV) cells. However, light intensity varies widely depending on location, rangi
ISSCC 2016
Session 21
Wireless
A Current-Mode Wireless Power Receiver with Optimal Resonant Cycle Tracking for Implantable Systems
to miniature implantable sensor systems such as [1]. To recharge batteries of such systems, wireless power transfer is a popular option since it is non-invasive. However, there are two main challenges: 1) strict safety r
ISSCC 2016
Session 21
Wireless
A 1.2cm2 2.4GHz Self-Oscillating RectifierAntenna Achieving -34.5dBm Sensitivity for Wirelessly Powered Sensors
Ubiquitous Internet-of-Everything (IoE) applications require low-cost, miniature sensors with long lifetimes. Wirelessly-powered ICs that harvest energy from an RF beacon or from existing wireless signals can address cha
ISSCC 2016
Session 21
Wireless
A 6.78MHz 6W Wireless Power Receiver with a 3-Level 1× / ½ × / 0× Reconfigurable Resonant Regulating Rectifier
devices to cut the last wire. Resonant wireless power transfer (R-WPT) using magnetic resonance emerges as a promising approach, as it provides spatial freedom and can charge multiple devices simultaneously. ISM-band fre
ISSCC 2016
Session 22
RF & Wireless
A 176-Channel 0.5cm3 0.7g Wireless Implant for Motor Function Recovery after Spinal Cord Injury
Brian Kim, Kuanfu Chen, Parag Gad, V. Reggie Edgerton, Wentai Liu University of California, Los Angeles, CA Epidural spinal stimulation has shown effectiveness in recovering the motor function of spinal cord transected r
ISSCC 2016
Session 22
RF & Wireless
A 141µW Sensor SoC on OLED/OPD Substrate for SpO2/ExG Monitoring Sticker
applications for broader light emission and low fabrication cost. In addition, Organic Photo Detector (OPD) and OLED can be fabricated on the same substrate with the same process and the OLED film itself can be used for