ISSCC 2019

2019

181 篇论文 · AI / ML (24) · Medical & Bio (21) · Wireline I/O (17) · Wireless (14) · Data Converters (14)

ISSCC 2019 Session 17 Medical & Bio
A 2.6µW Monolithic CMOS Photoplethysmographic Sensor Operating with 2µW LED Power
Antonino Caizzone, Assim Boukhayma, Christian Enz
Photoplethysmography (PPG) is a key technology allowing non-invasive monitoring of vital indicators such as heart rate (HR) and oxygen saturation (SpO2). Today, the total PPG sensor power consumption is dominated by the
EPFL, Neuchâtel, Switzerland
ISSCC 2019 Session 18 Analog Circuits
A -105dBc THD+N (-114dBc HD2) at 2.8VPP Swing and 120dB DR Audio Decoder with Sample-and-Hold Noise Filtering and Poly Resistor Linearization Schemes
Shon-Hang Wen, Kuan-Dar Chen, Chuan-Hung Hsiao, Ya-Chi Chen
Three major design issues that arise for high-fidelity audio decoders are: 1) DAC reference noise limiting achievable SNR [1,2]; 2) THD+N degradation at large output swing [3,4]; and 3) Distortion arising from limited amp
MediaTek, Hsinchu, Taiwan
ISSCC 2019 Session 18 Analog Circuits
A 16fJ/Conversion-Step Time-Domain Two-Step Capacitance-to-Digital Converter
Xiyuan Tang1, Shaolan Li1, Linxiao Shen1, Wenda Zhao1, Xiangxing Yang1,
Boston, MA 1 2 Capacitive sensors are widely used to measure various physical quantities, including pressure, humidity [1], and displacement [2]. Ultra-low-power capacitance-to-digital converters (CDCs) are required for
Randy Williams1, Jiaxin Liu2, Zhichao Tan3, Neal Hall1, Nan Sun1 Unive
ISSCC 2019 Session 18 Analog Circuits
An Auto-Zero Stabilized Voltage Buffer with a Quiet Chopping Scheme and Constant Input Current
Thije Rooijers, Johan H. Huijsing, Kofi A. A. Makinwa
The readout of high-impedance sensors and sampled voltage references [1] requires amplifiers that can achieve both low offset and low input current. Recently, it has been shown that this unique combination can be achieved
Delft University of Technology, Delft, The Netherlands
ISSCC 2019 Session 18 Analog Circuits
A 0.55nW/0.5V 32kHz Crystal Oscillator Based on a DC-Only Sustaining Amplifier for IoT
Hani Esmaeelzadeh, Sudhakar Pamarti
An always-ON, stable, 32kHz crystal oscillator (XO) provides key time-keeping, synchronization, and sleep-timer functions in most electronic systems. Ultra-low power (ULP) consumption of the XO is critical in highly duty
University of California, Los Angeles, CA
ISSCC 2019 Session 18 Analog Circuits
A 54MHz Crystal Oscillator with 30× Start-Up Time Reduction Using 2-Step Injection in 65nm CMOS
Karim M. Megawer1, Nilanjan Pal1, Ahmed Elkholy1, Mostafa G. Ahmed1,
bottleneck in reducing the average power of heavily duty-cycled wireless/wireline communication systems [1]. Among all the reported schemes to reduce TSTART, techniques that increase initial noise amplitude by injecting
Amr Khashaba1, Danielle Griffith2, Pavan Kumar Hanumolu1 University of
ISSCC 2019 Session 18 Analog Circuits
A 32MHz Crystal Oscillator with Fast Start-up Using Synchronized Signal Injection
Bram Verhoef1, Jan Prummel2, Wim Kruiskamp2, Rein Post2
Dialog Semiconductor, 's-Hertogenbosch, The Netherlands 1 2 Low-power sensor nodes (e.g. Bluetooth Low Energy, BLE) use low duty-cycle transceivers to obtain an overall low power consumption. The system typically spends
Dialog Semiconductor, Hengelo, The Netherlands
ISSCC 2019 Session 18 Analog Circuits
A 192pW Hybrid Bandgap-Vth Reference with Process Dependence Compensated by a Dimension-Induced Side-Effect
Youngwoo Ji, Jungho Lee, Byungsub Kim, Hong-June Park, Jae-Yoon Sim
various internal voltages. Since it consumes static power in standby modes, it plays an important role in energy management of battery-limited applications. The bandgap reference (BGR) has been a widely used approach sin
Pohang University of Science and Technology, Pohang, Korea A voltage r
ISSCC 2019 Session 19 Digital Circuits
Computationally Enabled Total Energy Minimization Under Performance Requirements for a VoltageRegulated 0.38-to-0.58V Microprocessor in 65nm CMOS
Fahim ur Rahman, Rajesh Pamula, Akshat Boora, Xun Sun, Visvesh Sathe
University of Washington, Seattle, WA Integrated circuits for ultra-low-power applications strive to minimize total system energy, while satisfying performance requirements. The supply voltage (Vdd) can be set to a Minim
ISSCC 2019 Session 19 Digital Circuits
A 6.4pJ/Cycle Self-Tuning Cortex-M0 IoT Processor Based on Leakage-Ratio Measurement for EnergyOptimal Operation Across Wide-Range PVT Variation
Jeongsup Lee1, Yiqun Zhang1, Qing Dong1, Wooteak Lim1,
Mehdi Saligane1, Yejoong Kim1, Seokhyeon Jeong1, Jongyup Lim1, Makoto Yasuda2, Satoru Miyoshi3, Masaru Kawaminami2,3, David Blaauw1, Dennis Sylvester1 University of Michigan, Ann Arbor, MI Mie Fujitsu Semiconductor Limit
ISSCC 2019 Session 19 Digital Circuits
A 7nm All-Digital Unified Voltage and Frequency Regulator Based on a High-Bandwidth 2-Phase Buck Converter with Package Inductors increasing the duty cycle to ~100% and maximizing the time for enabling the high side of the output stage. On the contrary, if FOUT speeds up with respect to FREF due to a large VOUT overshoot event, the duty cycle may reduce to ~0%, minimizing the time the high side of the output stage is enabled.
Francois Atallah1, Keith Bowman1, Hoan Nguyen1, Jihoon Jeong1,
Daniel Yingling1, Yu Sun1, Brad Appel1, Anthony Polomik1, Mahesh Harinath1, Joshua Morelli1, Thomas Moore1, Nathaniel Reeves2, Amer Cassier2, Arijit Raychowdhury3 The TRC oscillator enables the interdependent relationshi
ISSCC 2019 Session 19 Digital Circuits
An Adaptive Clock Management Scheme Exploiting Instruction-Based Dynamic Timing Slack for a GeneralPurpose Graphics Processor Unit with Deep Pipeline and Out-of-Order Execution
Tianyu Jia, Russ Joseph, Jie Gu
Cycle-by-cycle dynamic timing slack (DTS), which represents extra timing margin from the critical-path timing slack reported by the static timing analysis (STA), has been observed at both program level and instruction le
Northwestern University, Evanston, IL
ISSCC 2019 Session 19 Digital Circuits
Digital Leakage Compensation for a Low-Power and LowJitter 0.5-to-5GHz PLL in 10nm FinFET CMOS Technology
Yongping Fan, Bo Xiang, Dan Zhang, James S. Ayers,
loop (PLL) design [1] continues in the 10nm node and beyond, the leakage from various sources could become an issue in the applications where the reference clock frequency is low and the static phase error is required to
Kuan-Yueh James Shen, Andrey Mezhiba Intel, Hillsboro, OR As the push
ISSCC 2019 Session 19 Digital Circuits
A 40-to-80MHz Sub-4µW/MHz ULV Cortex-M0 MCU SoC in 28nm FDSOI with Dual-Loop Adaptive Back-Bias Generator for 20µs Wake-Up From Deep Fully Retentive Sleep Mode
David Bol1, Maxime Schramme1, Ludovic Moreau1, Thomas Haine1,
Pengcheng Xu1, Charlotte Frenkel1, Rémi Dekimpe1, François Stas2, Denis Flandre1 UCLouvain, Louvain-la-Neuve, Belgium e-peas semiconductors, Louvain-la-Neuve, Belgium 1 2 Near-threshold circuits operating at ultra-low vo
ISSCC 2019 Session 19 Digital Circuits
A Scalable Pipelined Time-Domain DTW Engine for Time-Series Classification Using Multibit Time Flip-Flops with 140Giga-Cell-Updates/s Throughput
Zhengyu Chen, Jie Gu
Dynamic time warping (DTW), a variant of the dynamic programming algorithm, is widely used for time series classification [1]. Its strong capability for distance measurement for variable-speed temporal sequences makes DTW
Northwestern University, Evanston, IL
ISSCC 2019 Session 2 Digital Processors
Summit and Sierra: Designing AI/HPC Supercomputers
James A. Kahle1, Jaime Moreno2, Dan Dreps3
IBM Research, Yorktown Heights, NY 3 IBM Systems and Technology, Austin, TX 1 2 The Summit and Sierra Supercomputer Systems, deployed in 2018 at the Department of Energy (DOE) National Laboratories, Oak Ridge (ORNL) and
IBM Research, Austin, TX
ISSCC 2019 Session 2 Digital Processors
A 978GOPS/W Flexible Streaming Processor for RealTime Image Processing Applications in 22nm FDSOI stream up to 1024 cycles, buffering up to one line of HD frames without chaining FIFOs together. Unused SRAM blocks are placed in sleep mode for the full execution duration to minimize power consumption.
Sander Smets1, Toon Goedemé1, Anurag Mittal2, Marian Verhelst1, Crucial to streaming fabrics is their ability to map and
of image processing compute kernels found in typical image processing pipelines, as listed in Fig. 2.2.1. Fig. 2.2.3 demonstrates how 3 of these kernels can be mapped on the presented fabric: horizontal and vertical Sobe
ISSCC 2019 Session 2 Digital Processors
An Energy-Efficient Configurable Lattice Cryptography Processor for the Quantum-Secure Internet of Things
Utsav Banerjee1, Abhishek Pathak2, Anantha P. Chandrakasan1
Indian Institute of Technology Delhi, New Delhi, India 1 2 Modern public key protocols, such as RSA and elliptic curve cryptography (ECC), will be rendered insecure by Shor’s algorithm [1] when large-scale quantum comput
Massachusetts Institute of Technology, Cambridge, MA
ISSCC 2019 Session 2 Digital Processors
A Distributed Autonomous and Collaborative Multi-Robot System Featuring a Low-Power Robot SoC in 22nm CMOS for Integrated Battery-Powered Minibots
Vinayak Honkote1, Dileep Kurian1, Sriram Muthukumar1, Dibyendu Ghosh1,
Satish Yada1, Kartik Jain1, Bradley Jackson2, Ilya Klotchkov2, Mallikarjuna Rao Nimmagadda1, Shreela Dattawadkar1, Pranjali Deshmukh1, Ankit Gupta1, Jaykant Timbadiya1, Ravi Pali1, Karthik Narayanan1, Saksham Soni1, Sara
ISSCC 2019 Session 2 AI / ML
A 40×40 Four-Neighbor Time-Based In-Memory Computing Graph ASIC Chip Featuring Wavefront Expansion and 2D Gradient Control
Luke R. Everson, Sachin S. Sapatnekar, Chris H. Kim
Single-source shortest path (SSP) problems have a rich history of algorithm development [1-3]. SSP has many applications including AI decision making, robot navigation, VLSI signal routing, autonomous vehicles and many o
University of Minnesota, Minneapolis, MN
ISSCC 2019 Session 2 AI / ML
A 2×30k-Spin Multichip Scalable Annealing Processor Based on a Processing-In-Memory Approach for Solving Large-Scale Combinatorial Optimization Problems
Takashi Takemoto1, Masato Hayashi2, Chihiro Yoshimura2, Masanao Yamaoka2
computer architecture, commonly known as annealing processor [1, 2]. An annealing processor provides a fast means for finding the ground state of an Ising model; thus, it can efficiently solve NP-hard combinatorial optimiz
Hitachi, Sapporo, Japan Hitachi, Tokyo, Japan 1 2 The last decade has
ISSCC 2019 Session 2 Digital Processors
A 28nm 600MHz Automotive Flash Microcontroller with Virtualization-Assisted Processor for Next-Generation Automotive Architecture Complying with ISO26262 ASIL-D
Sugako Otani, Norimasa Otsuki, Yasufumi Suzuki, Naoto Okumura,
Shohei Maeda, Tomonori Yanagita, Takao Koike, Yasuhisa Shimazaki, Masao Ito, Minoru Uemura, Toshihiro Hattori, Tadaaki Yamauchi, Hiroyuki Kondo Renesas Electronics, Kodaira, Japan Automotive architecture has been rapidly
ISSCC 2019 Session 20 Data Converters
A 5GS/s 7.2 ENOB Time-Interleaved VCO-Based ADC Achieving 30.5fJ/conv-step
Maarten Baert, Wim Dehaene
Technology scaling has been very beneficial for digital circuits both in terms of speed and power. Traditional analog techniques however are challenged by the ever-decreasing supply voltages. Highly digital VCO-based ADCs
KU Leuven, Heverlee, Belgium
ISSCC 2019 Session 20 Data Converters
A 40MHz-BW 320MS/s Passive Noise-Shaping SAR ADC with Passive Signal-Residue Summation in 14nm FinFET
Ying-Zu Lin*, Chin-Yu Lin*, Shan-Chih Tsou, Chih-Hou Tsai, Chao-Hsin Lu
applications due to their low power and small area. SNR of 60-70dB is necessary to meet the noise budget for the downlink chain in the 802.11 ac/ax standards. Comparator noise and quantization noise are typically the dom
MediaTek, Hsinchu, Taiwan *Equally-Credited Authors (ECAs) SAR ADCs ar
ISSCC 2019 Session 20 Data Converters
A 50MHz-Bandwidth 70.4dB-SNDR Calibration-Free Time-Interleaved 4th-Order Noise-Shaping SAR ADC
Lu Jie, Boyi Zheng, Michael P. Flynn
Noise-Shaping SAR (NS-SAR) is an emerging ADC architecture that offers both high resolution and high energy efficiency. State-of-the-art NS-SAR ADCs eliminate the need for op-amps, which relaxes design complexity and tech
University of Michigan, Ann Arbor, MI
ISSCC 2019 Session 20 Data Converters
An 8×-OSR 25MHz-BW 79.4dB/74dB DR/SNDR CT ΔΣ Modulator Using 7b Linearized Segmented DACs with Digital Noise-Coupling-Compensation Filter in 7nm FinFET CMOS
Tien-Yu Lo, Chan-Hsiang Weng, Hung-Yi Hsieh, Ting-Yang Wang,
block in a cellular receiver design. A continuous-time delta-sigma modulator (CTDSM), which gets the benefit of inherent anti-alias filtering, is a common architecture choice for the ADC. However, low power dissipation dic
Yun-Shiang Shu, Pao-Cheng Chiu MediaTek, Hsinchu, Taiwan A low-power a
ISSCC 2019 Session 20 Data Converters
A 76.6dB-SNDR 50MHz-BW 29.2mW Noise-CouplingAssisted CT Sturdy MASH ΔΣ Modulator with 1.5b/4b Quantizers in 28nm CMOS
Liang Qi1, Ankesh Jain2, Dongyang Jiang1, Sai-Weng Sin1,
Rui P. Martins1,3, Maurits Ortmanns2 University of Macau, Macau, China, University of Ulm, Ulm, Germany 3 Instituto Superior Tecnico/University of Lisboa, Lisbon, Portugal 1 2 The demands for wider cellular bandwidth (BW
ISSCC 2019 Session 20 Data Converters
An 80MHz-BW 31.9fJ/conv-step Filtering ΔΣ ADC with a Built-In DAC-Segmentation/ELD-Compensation 6b 960MS/s SAR-Quantizer in 28nm LP for 802.11ax Applications
Chi-Yun Wang, Jen-Huan Tsai, Sheng-Yuan Su, Jen-Che Tsai,
rate, which speeds up the development of the next-generation wireless-LAN (WLAN) standard. To improve spectrum efficiency and serve more users in crowded areas while increasing maximum throughput, 802.11ax supports 1024QA
Jhy-Rong Chen, Chih-Hong Lou MediaTek, Hsinchu, Taiwan The demand for
ISSCC 2019 Session 20 Data Converters
A 72.6dB-SNDR 100MHz-BW 16.36mW CTDSM with Preliminary Sampling and Quantization Scheme in Backend Subranging QTZ
Wei Wang1, Chi-Hang Chan1, Yan Zhu1, Rui P. Martins1,2
Instituto Superior Tecnico/University of Lisboa, Lisbon, Portugal 1 2 Driven by great demands for high data transfer rates in mobile communications, ADCs require wide bandwidths with low noise density and power consumpti
University of Macau, Macau, China
ISSCC 2019 Session 22 Medical & Bio
A 769µW Battery-Powered Single-Chip SoC with BLE for Multi-Modal Vital Sign Health Patches
Mario Konijnenburg1, Roland van Wegberg1, Shuang Song2,
Hyunsoo Ha1, Wim Sijbers2, Jiawei Xu1, Stefano Stanzione1, Chris van Liempd1, Dwaipayan Biswas2, Arjan Breeschoten1, Peter Vis1, Chris Van Hoof1,2,3, Nick Van Helleputte2 imec - Netherlands, Eindhoven, The Netherlands im
ISSCC 2019 Session 22 Medical & Bio
A Rugged Wearable Modular ExG Platform Employing a Distributed Scalable Multi-Channel FM-ADC Achieving 101dB Input Dynamic Range and Motion-Artifact Resilience
Julian Warchall1, Paul Theilmann2, Yuxuan Ouyang2, Harinath Garudadri1, Patrick P. Mercier1
University of California, San Diego, La Jolla, CA MaXentric Technologies, La Jolla, CA 1 2 Wearable ExG biopotential acquisition systems can potentially capture a wealth of clinically useful diagnostic information during
ISSCC 2019 Session 22 Medical & Bio
A 0.5V 9.26µW 15.28mΩ/√Hz Bio-Impedance Sensor IC with 0.55° Overall Phase Error
Kwantae Kim, Ji-Hoon Kim, Surin Gweon, Jiwon Lee, Minseo Kim,
measurement [1] is critical in reducing chronic heart failure (CHF) because the symptoms of deterioration are not recognized by patients, thus preventing timely treatment. Therefore, a wearable/implantable bio-impedance
Yongsu Lee, Soyeon Kim, Hoi-Jun Yoo KAIST, Daejeon, Korea Continuous b
ISSCC 2019 Session 22 Medical & Bio
A 27.8μW Biopotential Amplifier Tolerant to 30Vpp Common-Mode Interference for Two-Electrode ECG Recording in 0.18μm CMOS
Nahmil Koo, SeongHwan Cho
Two-electrode ECG devices have gained popularity in the recent past to enable comfortable and long-term monitoring of cardiovascular health. As a ground or bias electrode is not used in a two-electrode ECG device, common
KAIST, Daejeon, Korea
ISSCC 2019 Session 22 Medical & Bio
A Bio-Impedance Readout IC with Digital-Assisted Baseline Cancellation for 2-Electrode Measurement
imec - Netherlands, Eindhoven, The Netherlands
KU Leuven, Heverlee, Belgium Figure 22.5.3 compares the measured noise performance with and without baseline cancellation. All noise numbers are measured by applying a current to a known resistor and taking the digital o
imec, Heverlee, Belgium
ISSCC 2019 Session 22 Medical & Bio
A 13-Channel 1.53-mW 11.28-mm2 Electrical Impedance Tomography SoC Based on Frequency Division Multiplexing with 10× Throughput Reduction
Boxiao Liu1,2, Guoxing Wang1, Yongfu Li1, Hui Li1, Yue Gao1, Lei Zeng2,
has been reported as the only viable wearable real-time method for lung imaging [1]. Previous EIT chips generally employ Time-Division Multiplexing (TDM) or as active electrode to facilitate multichannel read-out [2-4],
Yixin Ma1, Yong Lian1, Chun Huat Heng2 Shanghai Jiao Tong University,
ISSCC 2019 Session 22 Medical & Bio
A Programmable Wireless EEG Monitoring SoC with Open/Closed-Loop Optogenetic and Electrical Stimulation for Epilepsy Control
Shuenn-Yuh Lee, Chieh Tsou, Peng-Wei Huang, Po-Hao Cheng,
stimulation systems [1-2] for efficient control of neurological disorders is increasing, because recent clinical studies have shown their efficiency and usefulness in symptom suppression. Electrical stimulation can produce
Chi-Chung Liao, Zhan-Xien Liao, Hao-Yun Lee, Chou-Ching Lin, Chia-Hsia
ISSCC 2019 Session 22 Medical & Bio
Adaptively Clock-Boosted Auto-Ranging Responsive Neurostimulator for Emerging Neuromodulation Applications
M. Reza Pazhouhandeh , Gerard O'Leary , Iliya Weisspapir ,
David Groppe2, Xuan-Thuan Nguyen1, Karim Abdelhalim1, 3, Hamed Mazhab Jafari1,4, Taufik A. Valiante5, Peter Carlen5, Naveen Verma6, Roman Genov1 *1 *1 2 University of Toronto, Toronto, Canada Krembil Neuroscience Center,
ISSCC 2019 Session 23 Memory
A 7.5Gb/s/pin LPDDR5 SDRAM with WCK Clocking and
Non-Target ODT for High Speed and with DVFS, Internal
Data Copy, and Deep-Sleep Mode for Low Power Kyung-Soo Ha, Chang-Kyo Lee, Dongkeon Lee, Daesik Moon, Jin-Hun Jang, Hyong-Ryol Hwang, Hyungjoon Chi, Junghwan Park, Seungjun Shin, Dukha Park, Sang-Yun Kim, Sukhyun Lim, Kiw
ISSCC 2019 Session 23 Memory
A 1.1V 1ynm 6.4Gb/s/pin 16Gb DDR5 SDRAM with a
Phase-Rotator-Based DLL, High-Speed SerDes and, RX/TX Equalization Scheme
write (MRW) setting. 3rd step is fine training, sweeping the DQS signal to find the rising edge of IWES. After the training, IWES and DQS are matched without any additional delay. Therefore, it saves the power consumption
ISSCC 2019 Session 23 Memory
A 3-bit/2UI 27Gb/s PAM-3 Single-Ended Transceiver Using One-Tap DFE for Next-Generation Memory Interface
Hyunsu Park1, Junyoung Song2, Yeonho Lee1, Jincheol Sim1,
high-data throughput while maintaining single-ended signaling and the supply voltage of I/O has been scaled down. Due to the increasing interface bandwidth the required area and power consumption has increased as well, r
Jonghyuck Choi1, Chulwoo Kim1 Korea University, Seoul, Korea Incheon N
ISSCC 2019 Session 23 Memory
A 512GB 1.1V Managed DRAM Solution with 16GB ODP and Media Controller
Seongju Lee, Byungdeuk Jeon, Kyeongpil Kang, Dongyoon Ka,
Nayeon Kim, Yongseop Kim, Yunseok Hong, Mankeun Kang, Jinyong Min, Mingyu Lee, Chunseok Jeong, Kwandong Kim, Doobock Lee, Junghyun Shin, Yuntack Han, Youngbo Shim, Youngjoo Kim, Yongsun Kim, Hyunseok Kim, Jaewoong Yun, B
ISSCC 2019 Session 24 AI / ML
A 1Mb Multibit ReRAM Computing-In-Memory Macro with 14.6ns Parallel MAC Computing Time for CNNBased AI Edge Processors
Cheng-Xin Xue, Wei-Hao Chen, Je-Syu Liu, Jia-Fang Li, Wei-Yu Lin,
Wei-En Lin, Jing-Hong Wang, Wei-Chen Wei, Ting-Wei Chang, Tung-Cheng Chang, Tsung-Yuan Huang, Hui-Yao Kao, Shih-Ying Wei, Yen-Cheng Chiu, Chun-Ying Lee, Chung-Chuan Lo, Ya-Chin King, Chorng-Jung Lin, Ren-Shuo Liu, Chih-C
ISSCC 2019 Session 24 Memory
A 7nm 2.1GHz Dual-Port SRAM with WL-RC Optimization and Dummy-Read-Recovery Circuitry to Mitigate ReadDisturb-Write Issue
Hidehiro Fujiwara, Chih-Yu Lin, Hsien-Yu Pan, Cheng-Han Lin,
and wire routing resistance and capacitance; it degrades SRAM performance and results in SRAM design difficulties. Although dual-port (DP) SRAM is useful, because it can offer simultaneous read and write operations with t
Po-Yi Huang, Kao-Cheng Lin, Jhon-Jhy Liaw, Yen-Huei Chen, Hung-Jen Lia
ISSCC 2019 Session 24 Memory
A Voltage and Temperature Tracking SRAM Assist Supporting 740mV Dual-Rail Offset for Low-Power and High-Performance Applications in 7nm EUV FinFET Technology
Inhak Lee, Hanwool Jeong, Sangyeop Baeck, Siddharth Gupta,
Changnam Park, Dongwook Seo, Jaesung Choi, Jaeyoung Kim, Hoon Kim, Jungmyung Kang, Sunyung Jang, Daeyoung Moon, Sangshin Han, Taehyung Kim, Jaehyun Lim, Younghwan Park, Hyejin Hwang, Jeonseung Kang, Jaeseung Choi, Taejoo
ISSCC 2019 Session 24 Memory
Sandwich-RAM: An Energy-Efficient In-Memory BWN Architecture with Pulse-Width Modulation
Jun Yang1, Yuyao Kong1, Zhen Wang2, Yan Liu1, Bo Wang1, Shouyi Yin3, Longxin Shi1
state-of-the-art results in the field of visual perception, drastically changing the traditional computer-vision framework. However, the movement of massive amounts of data prevents CNN’s from being integrated into low-po
Southeast University, Nanjing, China Boxing Electronics, Nanjing, Chin
ISSCC 2019 Session 24 AI / ML
A Twin-8T SRAM Computation-In-Memory Macro for Multiple-Bit CNN-Based Machine Learning
Xin Si1,2, Jia-Jing Chen1, Yung-Ning Tu1, Wei-Hsing Huang1,
Jing-Hong Wang1, Yen-Cheng Chiu1, Wei-Chen Wei1, Ssu-Yen Wu1, Xiaoyu Sun3, Rui Liu3, Shimeng Yu4, Ren-Shuo Liu1, Chih-Cheng Hsieh1, Kea-Tiong Tang1, Qiang Li2, Meng-Fan Chang1 National Tsing Hua University, Hsinchu, Taiw
ISSCC 2019 Session 25 Hardware Security
A 562F2 Physically Unclonable Function with a Zero-Overhead Stabilization Scheme
Dai Li, Kaiyuan Yang
Internet of Things (IoT) devices bring a growing demand for secure, low-power, and low-cost secret key and ID storage solutions. Physically unclonable functions (PUFs) are one of the most promising alternatives to conven
Rice University, Houston, TX
ISSCC 2019 Session 25 Hardware Security
A Reconfigurable RRAM Physically Unclonable Function Utilizing Post-Process Randomness Source with <6×10-6 Native Bit Error Rate
Yachuan Pang1, Bin Gao1, Dong Wu1, Shengyu Yi1, Qi Liu1,
Wei-Hao Chen2, Ting-Wei Chang2, Wei-En Lin2, Xiaoyu Sun3, Shimeng Yu3, He Qian1, Meng-Fan Chang2, Huaqiang Wu1 Tsinghua University, Beijing, China National Tsing Hua University, Hsinchu, Taiwan 3 Georgia Institute of Tec
ISSCC 2019 Session 25 Hardware Security
A 128b AES Engine with Higher Resistance to Power and Electromagnetic Side-Channel Attacks Enabled by a Security-Aware Integrated All-Digital Low-Dropout Regulator
Arvind Singh1, Monodeep Kar2, Sanu Mathew2, Anand Rajan2, Vivek De2, Saibal Mukhopadhyay1
information leakage through power consumption and electromagnetic (EM) emissions from cryptographic engines to uncover secret keys. Integrated inductive voltage regulators (IVR) with a randomized control loop [1] or swit
Georgia Institute of Technology, Atlanta, GA Intel, Hillsboro, OR 1 2
ISSCC 2019 Session 26 RF & Wireless
A Self-Calibrated 16GHz Subsampling-PLL-Based 30µs Fast Chirp FMCW Modulator with 1.5GHz Bandwidth and 100kHz rms Error
Qixian Shi1, Keigo Bunsen2, Nereo Markulic1, Jan Craninckx1
Sony Semiconductor Solutions, Atsugi, Japan 1 2 Frequency-modulated continuous-wave (FMCW) radars are critical for autonomous-driving applications. Sawtooth waveforms with short chirp time (<50μs) are desired to eliminat
imec, Heverlee, Belgium