ISSCC 2020

2020

202 篇论文 · Power Management (24) · RF & Wireless (23) · AI / ML (20) · Analog Circuits (16) · Medical & Bio (16)

ISSCC 2020 Session 18 Power Management
A Monolithic E-Mode GaN 15W 400V Offline Self-Supplied Hysteretic Buck Converter with 95.6% Efficiency
Maik Kaufmann1, Michael Lueders2, Cetin Kaya3, Bernhard Wicht1
Texas Instruments, Freising, Germany, 3 Texas Instruments, Dallas, TX 1 2 Due to superior figures-of-merit (FoMs), gallium nitride (GaN) high-electron mobility transistors (HEMTs) offer a huge potential for high-voltage
Leibniz University Hannover, Hannover, Germany
ISSCC 2020 Session 18 Power Management
A 120mA Non-Isolated Capacitor-Drop AC/DC Power Supply
Yogesh Ramadass*1, Andres Blanco*2, Boqiang Xiao*3, John Cummings3, *Equally-Credited Authors (ECAs)
meters, appliances, smoke alarms to ground fault detectors require a non-isolated DC supply that is powered directly from the AC mains. These applications typically require the ability to handle up to 305VAC,rms at the i
Texas Instruments, Santa Clara, CA, 2Texas Instruments, Dallas, TX Tex
ISSCC 2020 Session 18 Power Management
An 11MHz Fully Integrated 5kV Isolated DC-DC Converter Without Cross-Isolation-Barrier Feedback
Lisong Li1, Xiangming Fang1, Rongxiang Wu2
University of Electronic Science and Technology of China, Chengdu, China 1 2 Galvanic isolation greatly enhances system safety and reliability in applications such as medical devices and sensor interfaces. In these appli
CoilEasy Technologies, Chongqing, China
ISSCC 2020 Session 18 Power Management
ZVS Flyback-Converter ICs Optimizing USB Power Delivery for Fast-Charging Mobile Devices to Achieve 93.5% Efficiency
Wei-Hsu Chang, Kun-Yu Lin, Chun-Ching Lee, Li-Di Lo, Jenn-Yu Lin, Ta-Yung Yang
standard as a charging solution for mobile devices [1]. Moreover, the extended specification includes programmable power supply (PPS) which is suitable for fast charging mobile devices by allowing the power source to dyn
Richtek, Hsinchu, Taiwan USB power delivery (PD) supporting up to 100W
ISSCC 2020 Session 18 Power Management
A 92.8%-Peak-Efficiency 60A 48V-to-1V 3-Level Half-Bridge DC-DC Converter with Balanced Voltage on a Flying Capacitor
Minho Choi1,2, Deog-Kyoon Jeong1
Samsung Electronics, Hwaseong, Korea 1 2 Demand for DC-DC voltage conversion from a 48V input has been on the rise due to proliferation of server and automotive applications with a 48V intermediate bus and 48V batteries,
Seoul National University, Seoul, Korea
ISSCC 2020 Session 18 Power Management
A DC to 35MHz Fully Integrated Single-Power-Supply Isolation Amplifier for Current- and Voltage-Sensing Front-Ends of Power Electronics
Satoshi Takaya, Hiroaki Ishihara, Kohei Onizuka
Increased switching frequency of power devices for power electronics allows for compact and lightweight circuit implementations for variety of applications, including power factor corrections, DC/DC converters, and motor
Toshiba, Kawasaki, Japan
ISSCC 2020 Session 18 AI / ML
A Fully-Generic-Process Galvanic Isolator for Gate Driver with 123mW 23% Power Transfer and Full-Triplex 21/14/0.5Mb/s Bidirectional Communication Utilizing Reference-Free Dual-Modulation FSK DATA2 is transferred in the same manner as DATA1 through another transformer. Almost all the circuits excluding the DATA1 driver and I/O buffer operate at 1.5V supply to support sufficiently high operating speed. The driver operates with 5.5V supply to transfer power by the same transformer, and the rectifier placed in parallel with the DATA1 receiver extracts the received power.
Hiroaki Ishihara, Kohei Onizuka, Figure 18.8.3 explains the operation of the error-tolerant DATA1 demodulator.
Thanks to the VCO synchronization, demodulation can be realized by a delaybased digital frequency counting normalized by the oscillation period (tVCO). But there is a challenge in that the received signal edge is not per
ISSCC 2020 Session 19 Quantum & Photonics
A Scalable Cryo-CMOS 2-to-20GHz Digitally Intensive Controller for 4×32 Frequency Multiplexed Spin Qubits/Transmons in 22nm FinFET Technology for Quantum Computers
Bishnu Patra*1, Jeroen P. G. van Dijk*1, Sushil Subramanian2,
Andrea Corna1, Xiao Xue1, Charles Jeon2, Farhana Sheikh2, Esdras Juarez-Hernandez3, Brando Perez Esparza3, Huzaifa Rampurawala2, Brent Carlton2, Nodar Samkharadze4, Surej Ravikumar2, Carlos Nieva2, Sungwon Kim2, Hyung-Ji
ISSCC 2020 Session 19 Quantum & Photonics
A 110mK 295µW 28nm FDSOI CMOS Quantum Integrated Circuit with a 2.8GHz Excitation and nA Current Sensing of an On-Chip Double Quantum Dot
Loïck Le Guevel1,2, Gérard Billiot1, Xavier Jehl2, Silvano De Franceschi2,
Marcos Zurita1, Yvain Thonnart1, Maud Vinet1, Marc Sanquer2, Romain Maurand2, Aloysius G. M. Jansen2, Gaël Pillonnet1 CEA-LETI-MINATEC, Grenoble, France CEA-IRIG, Grenoble, France 1 2 To reach quantum supremacy, quantum
ISSCC 2020 Session 19 Quantum & Photonics
A 200dB FoM 4-to-5GHz Cryogenic Oscillator with an Automatic Common-Mode Resonance Calibration for Quantum Computing Applications
Jiang Gong1, Yue Chen1, Fabio Sebastiano1, Edoardo Charbon2,3, Masoud Babaie1
generation is required for the control electronics of quantum computers. To avoid limiting the performance of quantum bits, the frequency noise of a PLL should be <1.9kHzrms [1]. However, it is challenging for RF oscilla
Delft University of Technology, Delft, The Netherlands EPFL, Lausanne,
ISSCC 2020 Session 2 Digital Processors
Zen 2: The AMD 7nm Energy-Efficient High-Performance x86-64 Microprocessor Core
Teja Singh1, Sundar Rangarajan1, Deepesh John1, Russell Schreiber1,
design, fabricated in an energy-efficient TSMC 7nm FinFET process. Similar to AMD’s prior-generation core, codenamed “Zen” [1], the Core Complex Unit (CCX) with 4 cores in this version (Fig. 2.1.1) is used across a wide
Spence Oliver1, Rajit Seahra2, Alex Schaefer1 AMD, Austin, TX, 2AMD, M
ISSCC 2020 Session 2 Digital Processors
AMD Chiplet Architecture for High-Performance Server and Desktop Products
Samuel Naffziger1, Kevin Lepak2, Milam Paraschou1, Mahesh Subramony2
AMD, Austin, TX 1 2 AMD’s “Rome” and “Matisse” are second-generation AMD Infinity Fabric-based SoCs using 3 unique hybrid process technology chiplets to achieve leading performance, performance/$ and performance/W, targe
AMD, Fort Collins, CO
ISSCC 2020 Session 2 Digital Processors
A 220GOPS 96-Core Processor with 6 Chiplets 3D-Stacked on an Active Interposer Offering 0.6ns/mm
Latency, 3Tb/s/mm2 Inter-Chiplet Interconnects and, 156mW/mm2 @ 82%-Peak-Efficiency DC-DC Converters
which is finally delivered to the chiplet through a micro-bump face-to-face power grid (Fig. 2.3.7). The SCVR input voltage (up to 2.5V) reduces total input current and the required number of power IOs in the package. Ea
ISSCC 2020 Session 2 Digital Processors
A 7nm High-Performance and Energy-Efficient Mobile Application Processor with Tri-Cluster CPUs and a Sparsity-Aware NPU
Young Duk Kim, Wookyeong Jeong, Lakkyung Jung, Dongsuk Shin,
Jae Geun Song, Jinook Song, Hyeokman Kwon, Jaeyoung Lee, Jaesu Jung, Myungjin Kang, Jaehun Jeong, Yoonjoo Kwon, Nak Hee Seong Samsung Electronics, Hwaseong, Korea Mobile application processors (APs) must be extremely pow
ISSCC 2020 Session 2 Digital Processors
A 7nm FinFET 2.5GHz/2.0GHz Dual-Gear Octa-Core CPU Subsystem with Power/Performance Enhancements for a Fully Integrated 5G Smartphone SoC.
Hugh Mair1, Ericbill Wang2, Ashish Nayak1, Rolf Lagerquist1, Loda Chou2,
Gordon Gammie1, Hsinchen Chen1, Lee-Kee Yong1, Manzur Rahman1, Jenny Wiedemeier1, Ramu Madhavaram1, Alex Chiou2, Blundt Li2, Vincent Lin2, Rory Huang2, Michael Yang2, Achuta Thippana1, Osric Su2, SA Huang2 MediaTek, Aust
ISSCC 2020 Session 2 Digital Processors
A 16nm 3.5B+ Transistor >14TOPS 2-to-10W Multicore SoC Platform for Automotive and Embedded
Applications with Integrated Safety MCU, 512b Vector
VLIW DSP, Embedded Vision and Imaging Acceleration Rama Venkatasubramanian1, Don Steiss1, Greg Shurtz2, Tim Anderson1, Kai Chirca1, Raghavendra Santhanagopal1, Niraj Nandan1, Anish Reghunath1, Hetul Sanghvi1, Daniel Wu1,
ISSCC 2020 Session 2 Digital Processors
IBM z15: A 12-Core 5.2GHz Microprocessor
Christopher Berry1, Brian Bell2, Adam Jatkowski1, Jesse Surprise1,
John Isakson3, Ofer Geva1, Brian Deskin4, Mark Cichanowski3, Dina Hamid1, Chris Cavitt1, Gregory Fredeman1, Anthony Saporito1, Ashutosh Mishra5, Alper Buyuktosunoglu6, Tobias Webel7, Preetham Lobo5, Pradeep Parashurama5,
ISSCC 2020 Session 20 Power Management
A 28µW IoT Tag That Can Communicate with Commodity WiFi Transceivers via a Single-Side-Band QPSK Backscatter Communication Technique
Po-Han Peter Wang1,2, Chi Zhang1, Hongsen Yang1, Dinesh Bharadia1, Patrick P. Mercier1
San Diego, CA 1 2 Nearly all IoT devices require wireless connectivity, and to keep costs down and deployment opportunities up, communication should ideally occur with widely deployed commodity hardware such as WiFi. How
University of California, San Diego, La Jolla, CA Broadcom Inc
ISSCC 2020 Session 20 Power Management
A 57nW Software-Defined Always-On Wake-Up Chip for IoT Devices with Asynchronous Pipelined Event-Driven Architecture and Time-Shielding Level-Crossing ADC
Zhixuan Wang1, Le Ye1,2, Hao Zhang1, Jiayoon Ru3, Haitao Fan2,
China 1 2 IoT devices usually operate in random-sparse-event scenarios (Fig. 20.2.1). To avoid missing events, traditionally a periodic-wake-up frequency [1] must be orders of magnitude higher than the average event rate
Yangyuan Wang1, Ru Huang1 Peking University, Beijing, China Advanced I
ISSCC 2020 Session 20 Power Management
A 4.0×3.7×1.0mm3-MEMS CMOS Integrated E-Nose with
Embedded 4×Gas Sensors, a Temperature Sensor and, a Relative Humidity Sensor
Si Hoon Lee1, Kwangmin Park1, Jaeheung Lim1, Minchul Lee1, Jeongho Park1, Hyun Kim1, Young Ok Lee2, Hyun Su Ahn2, Eunseok Shin1, Hyungjong Ko1, Seoungjae Yoo1, Hyunsurk Ryu1, Yongin Park1, Joonseok Kim1, Long Yan1 Samsun
ISSCC 2020 Session 20 Power Management
3D Surgical Alignment with 100µm Resolution Using Magnetic-Field Gradient-Based Localization
Saransh Sharma, Grace Ding, Aditya Telikicherla, Fatemeh Aghlmand,
Arian Hashemi Talkhooncheh, Minwo Wang, Mikhail G. Shapiro, Azita Emami California Institute of Technology, Pasadena, CA Substantial advances in the field of surgery have taken place in recent years, which aim at decreas
ISSCC 2020 Session 21 Digital Processors
A Fully Integrated Genetic Variant Discovery SoC for Next-Generation Sequencing
Yi-Chung Wu*1, Yen-Lung Chen*1, Chung-Hsuan Yang1, Chao-Hsi Lee2,
Chao-Yang Yu3, Nian-Shyang Chang3, Ling-Chien Chen3, Jia-Rong Chang3, Chun-Pin Lin3, Hung-Lieh Chen3, Chi-Shi Chen3, Jui-Hung Hung2, Chia-Hsiang Yang1 National Taiwan University, Taipei, Taiwan National Chiao Tung Univer
ISSCC 2020 Session 21 Digital Processors
A 1.5µJ/Task Path-Planning Processor for 2D/3D Autonomous Navigation of Micro Robots
Chieh Chung, Chia-Hsiang Yang
Autonomous micro robots have been deployed for various applications, ranging from unmanned package delivery to smart aerial surveillance. These robots possess intelligence for perception, make decisions based on the coll
National Taiwan University, Taipei, Taiwan
ISSCC 2020 Session 21 Digital Processors
A 5.69mm2 0.98nJ/Pixel Image-Processing SoC with 24b High-Dynamic-Range and Multiple Sensor Format Support for Automotive Applications
Chi-Cheng Ju, Tsu-Ming Liu, Yung-Chang Chang, Chih-Ming Wang,
Chang-Hung Tsai, Ying-Jui Chen, TH Wu, Hue-Min Lin, Han-Liang Chou, Abrams Chen, Andy-HB Wang, WC Gu, Wayne Hsieh, Jing-Ying Chang, Shou-Chun Liao, CT Ho, Larry Chu, Sokonisa Wei, CH Wang, Kevin Jou MediaTek, Hsinchu, Ta
ISSCC 2020 Session 22 Memory
A 1.1V 16GB 640GB/s HBM2E DRAM with a Data-Bus Window-Extension Technique and a Synergetic On-Die ECC Scheme
Chi-Sung Oh, Ki Chul Chun, Young-Yong Byun, Yong-Ki Kim,
So-Young Kim, Yesin Ryu, Jaewon Park, Sinho Kim, Sanguhn Cha, Donghak Shin, Jungyu Lee, Jong-Pil Son, Byung-Kyu Ho, Seong-Jin Cho, Beomyong Kil, Sungoh Ahn, Baekmin Lim, Yongsik Park, Kijun Lee, Myung-Kyu Lee, Seungduk B
ISSCC 2020 Session 22 Memory
A 128Gb 8-High 512GB/s HBM2E DRAM with a Pseudo
Quarter Bank Structure, Power Dispersion and an, Instruction-Based At-Speed PMBIST
Dong Uk Lee, Ho Sung Cho, Jihwan Kim, Young Jun Ku, Sangmuk Oh, Chul Dae Kim, Hyun Woo Kim, Woo Young Lee, Tae Kyun Kim, Tae Sik Yun, Min Jeong Kim, SeungGyeon Lim, Seong Hee Lee, Byung Kuk Yun, Jun Il Moon, Ji Hwan Park
ISSCC 2020 Session 22 Memory
A 32Gb/s Digital-Intensive Single-Ended PAM-4 Transceiver for High-Speed Memory Interfaces Featuring a 2-Tap Time-Based Decision Feedback Equalizer and an In-Situ Channel-Loss Monitor
Po-Wei Chiu, Chris Kim
Single-ended transceivers that can deliver high-data rates at reduced supply voltages are required to meet the ever-growing demands of future memory interfaces. The performance of conventional non-return-to-zero (NRZ) li
University of Minnesota, Minneapolis, MN
ISSCC 2020 Session 22 Memory
An 8nm 18Gb/s/pin GDDR6 PHY with TX Bandwidth Extension and RX Training Technique
Soo-Min Lee, Kihwan Seong, Joohee Shin, Hyoungjoong Kim,
Jaehyun Jeong, Shinyoung Yi, Juyoung Kim, Eunsu Kim, Sukhyun Jung, Sangyun Hwang, Jihun Oh, Kwanyeob Chae, Kyoung-Hoi Koo, Sanghune Park, Jongshin Shin, Jaehong Park Samsung Electronics, Hwaseong, Korea Recent emerging a
ISSCC 2020 Session 22 Memory
A 0.8-to-2.3GHz Quadrature Error Corrector with Correctable Error Range of 101.6ps Using Minimum Total Delay Tracking and Asynchronous Calibration On-Off Scheme for DRAM Interface
Soyeong Shin1, Han-Gon Ko1, Sungchun Jang2, Dongkyun Kim2, Deog-Kyoon Jeong1
paths also increase. Thus, multiphase clocks are typically utilized in DRAMs to relax timing margins because of the reduced timing budget. However, phase errors between multiphase clocks, due to device mismatch, degrade
Seoul National University, Seoul, Korea SK hynix, Icheon, Korea 1 2 As
ISSCC 2020 Session 23 Analog Circuits
A 4GS/s 80dB DR Current-Domain Analog Front-End for Phase-Coded Pulse-Compression Direct Time-of-Flight Automotive LiDAR
Mahdi Kashmiri, Behnam Behroozpour, Vladimir Petkov,
Ken Wojciechowski, Christoph Lang Robert Bosch, Sunnyvale, CA LiDARs enable long-distance ranging at high spatial resolution and moderate computational effort. Pulsed-LiDARs measuring the direct-time-of-flight (dTOF) per
ISSCC 2020 Session 23 Analog Circuits
A 70µW 1.19mm2 Wireless Sensor with 32 Channels of Resistive and Capacitive Sensors and Edge-Encoded PWM UWB Transceiver
Yuxuan Luo, Yida Li, Aaron Voon-Yew Thean, Chun-Huat Heng
Emerging wireless multi-channel resistive and capacitive (RC) sensor interface circuits provide opportunities for various applications such as environmental monitoring [1], wearable [2] and human-computer interaction [3]
National University of Singapore, Singapore, Singapore
ISSCC 2020 Session 23 Analog Circuits
A 0-to-60V-Input VCM Coulomb Counter with SignalDependent Supply Current and ±0.5% Gain Inaccuracy from -50°C to 125°C Caspar van Vroonhoven
Analog Devices, Ismaning, Germany, Most battery-powered systems require measurement of the battery's state of
charge, (SOC). A straightforward way to determine SOC is to keep track of the current flowing in and out of a battery, a method known as coulomb counting. Compared to other methods such as voltage or impedance monitoring
ISSCC 2020 Session 23 Analog Circuits
A 28W -108.9dB/-102.2dB THD/THD+N Hybrid ΔΣ-PWM Class-D Audio Amplifier with 91% Peak Efficiency and Reduced EMI Emission around two-stage feedforward OTAs which together draw 1.8mA from a 1.8V supply. This combination of multilevel quantization together with a high fS results in a loop gain of >76dB (26dB higher than [6]) in the audio band irrespective of process spread, thus ensuring high linearity.
Shoubhik Karmakar1, Huajun Zhang1, Robert Van Veldhoven2,
Lucien Breems2, Marco Berkhout3, Qinwen Fan1, Kofi A.A. Makinwa1 The fully differential H-bridge output stage is shown in Fig. 23.4.1. It consists of four identical N-LDMOS devices (MH and ML) with an RON of ~100m$, whic
ISSCC 2020 Session 23 Analog Circuits
A 0.41mA Quiescent Current, 0.00091% THD+N ClassD Audio Amplifier with Frequency Equalization for PWMResidual-Aliasing Reduction
Shih-Hsiung Chien, Tai-Haur Kuo, Hung-Yi Huang, Hong-Bin Wang, Yi-Zhi Qiu
a pulse-width-modulation (PWM) modulator and a switching power stage is commonly adopted since it effectively suppresses the power-stage nonlinearity to improve total harmonic distortion plus noise (THD+N). However, unle
National Cheng Kung University, Tainan, Taiwan For Class-D audio ampli
ISSCC 2020 Session 23 Analog Circuits
A 2pA/√Hz Transimpedance Amplifier for Miniature Ultrasound Probes with 36dB Continuous-Time Gain Compensation
Eunchul Kang1, Mingliang Tan1, Jae-Sung An1, Zu-yao Chang1,
ultrasound probes, such as the intra-cardiac echography (ICE) probe shown in Fig. 23.6.1, increasingly employ in-probe ASICs to interface with the elements of an ultrasound transducer array to improve signal quality and
Philippe Vince2, Nicolas Sénégond2, Tony Mateo2, Cyril Meynier 2, Mich
ISSCC 2020 Session 23 Analog Circuits
A 130dB CMRR Instrumentation Amplifier with Common-Mode Replication
Sanfeng Zhang, Chen Gao, Xiong Zhou, Qiang Li
Interfacing with high-impedance sensors, such as dry-contacted electrodes and accelerometers requires high CMRR with sufficient input impedance concurrently. From the system point of view, the total CMRR (TCMRR) is deter
University of Electronic Science and Technology of China, Chengdu, Chi
ISSCC 2020 Session 23 Analog Circuits
A 41µW 16MS/s 99.2dB-SFDR Capacitively Degenerated Dynamic Amplifier with Nonlinear-Slope-Factor Compensation
Yunhong Kim1,2, Sungsik Park1,2, Seungwoo Song1, Sangwoo Lee1,
performance in analog front-ends and ADCs must have sufficiently low noise and high linearity to achieve overall system performance targets. Achieving the target noise level requires a certain amount of power, but nonlin
MoonHyung Jang1, Changuk Lee1, Youngcheol Chae1 Yonsei University, Seo
ISSCC 2020 Session 24 AI / ML
A 24-to-30GHz Watt-Level Broadband Linear Doherty Power Amplifier with Multi-Primary Distributed-ActiveTransformer Power-Combining Supporting 5G NR FR2 64-QAM with >19dBm Average Pout and >19% Average PAE
Fei Wang, Hua Wang
The continuous worldwide demand for multi-Gb/s data-rate has driven the rapid development and standardization of 5G New Radio (NR) specifications in the mmwave bands [1-3]. As a result, there is a surge of interest in hi
Georgia Institute of Technology, Atlanta, GA
ISSCC 2020 Session 24 RF & Wireless
A Reconfigurable Series/Parallel Quadrature-CouplerBased Doherty PA in CMOS SOI with VSWR Resilient Linearity and Back-Off PAE for 5G MIMO Arrays
assumption and vice versa. However, the design equations for Main/Aux-PA
reconfigurations remain the same. In addition, the Main/Aux-PAs role exchange for series/parallel Doherty operation is enabled by setting the bias of two adaptive biasing circuits. Naga Sasikanth Mannem, Min-Yu Huang, Tz
ISSCC 2020 Session 24 RF & Wireless
A 28GHz Current-Mode Inverse-Outphasing Transmitter Achieving 40%/31% PA Efficiency at Psat/6dB PBO and Supporting 15Gbit/s 64-QAM for 5G Communication
Sensen Li, Min-Yu Huang, Doohwan Jung, Tzu-Yuan Huang, Hua Wang
As mm-wave offers broader spectra and proportionate capacity increase, it will be extensively employed in 5G-and-beyond communication systems to address the exponentially growing data-rate demand. Viable mm-wave TX or PA
Georgia Institute of Technology, Atlanta, GA
ISSCC 2020 Session 24 RF & Wireless
A Watt-Level Multimode Multi-Efficiency-Peak Digital Polar Power Amplifier with Linear Single-Supply ClassG Technique
Si-Wook Yoo, Shih-Chang Hung, Sang-Min Yoo
Signals for next-generation communication systems typically have high peak-toaverage power ratios (PAPR) (e.g., 10 to 13dB), forcing operation at deep output power backoff (PBO). A good efficiency at PBO is required to m
Michigan State University, East Lansing, MI
ISSCC 2020 Session 24 AI / ML
A 15b Quadrature Digital Power Amplifier with Transformer-Based Complex-Domain Power-Efficiency Enhancement
Diyang Zheng, Yun Yin, Yiting Zhu, Liang Xiong, Yicheng Li, Na Yan, Hongtao Xu
law to provide compact die area, better interface to digital back-end, and higher power efficiency due to the faster switching nature of core devices even in face of reduced supply voltages. Moreover, the integration of
Fudan University, Shanghai, China With CMOS processes scaling down, di
ISSCC 2020 Session 24 RF & Wireless
An Instantaneously Broadband Ultra-Compact Highly Linear PA with Compensated Distributed-Balun Output Network Achieving >17.8dBm P1dB and >36.6% PAEP1dB over 24 to 40GHz and Continuously Supporting 64-/256-QAM 5G NR Signals over 24 to 42GHz
Fei Wang, Hua Wang
5G communication promises 10× to 100× data-rate increase to radically change future wireless connectivity. Millimeter-wave (mm-wave) bands can potentially deliver extreme data rates and capacity compared to low-GHz bands
Georgia Institute of Technology, Atlanta, GA
ISSCC 2020 Session 24 RF & Wireless
A 15dBm 12.8%-PAE Compact D-Band Power Amplifier with Two-Way Power Combining in 16nm FinFET CMOS
Bart Philippe, Patrick Reynaert
The drive for higher data-rates has led to the allocation of the spectrum above 100GHz for D-band communication. A high level of integration in a nm-CMOS technology is necessary to keep the cost low and allow for efficie
KU Leuven, Leuven, Belgium
ISSCC 2020 Session 24 RF & Wireless
A W-Band Power Amplifier with Distributed CommonSource GaN HEMT and 4-Way Wilkinson-Lange Combiner Achieving 6W Output Power and 18% PAE at 95GHz
Weibo Wang1,2, Fangjin Guo2, Tangsheng Chen2, Keping Wang1
Science and Technology on Monolithic Integrated Circuits and Modules Laboratory, Nanjing, China 1 2 W-band power amplifiers (PAs) play an important role in Gb/s-data-rate wireless communication, imaging, and radar applic
Tianjin University, Tianjin, China
ISSCC 2020 Session 25 Digital Circuits
A Fully Synthesizable Distributed and Scalable All-Digital LDO in 10nm CMOS
Suyoung Bang, Wootaek Lim, Charles Augustine, Andres Malavasi,
regulation for digital IP blocks. A distributed LDO architecture, where a number of dispersed LDO units supply a single domain with shared power delivery network (PDN), has been recently proposed for point-of-load regula
Muhammad Khellah, James Tschanz, Vivek De Intel, Hillsboro, OR Integra
ISSCC 2020 Session 25 Digital Circuits
A 480mA Output-Capacitor-Free Synthesizable Digital LDO Using CMP-Triggered Oscillator and Droop Detector
with 99.99% Current Efficiency, 1.3ns Response Time, and 9.8A/mm2 Current Density
intellectual properties (IPs) for better energy efficiency in a system-on-chip design
Jonghyun Oh, Jun-Eun Park, Young-Ha Hwang, Deog-Kyoon Jeong Seoul Nati
ISSCC 2020 Session 25 Digital Circuits
A 65nm Edge-Chasing Quantizer-Based Digital LDO Featuring 4.58ps-FoM and Side-Channel-Attack Resistance
Yan He, Kaiyuan Yang
Low-Dropout Regulators (LDOs) are commonly desired for fine-grained power management in SoCs because of their compact area, high current efficiency, and small output ripple. Digital LDOs (DLDOs) are increasingly adopted
Rice University, Houston, TX
ISSCC 2020 Session 25 Digital Circuits
A Scalable 20GHz On-Die Power-Supply Noise Analyzer with Compressed Sensing
Pengfei Zhai, Xiong Zhou, Yan Cai, Zheng Zhu, Fan Zhang, Qiang Li
Power-supply noise (PSN) is a key consideration that determines the performance, as well as functionality of ICs, especially for modern SoCs with significantly increased scale, level of integration, and sophisticated vol
University of Electronic Science and Technology of China, Chengdu, Chi
ISSCC 2020 Session 25 Digital Circuits
A Self-Calibrated 1.2-to-3.8GHz 0.0052mm2 Synthesized Fractional-N MDLL Using a 2b Time-Period Comparator in 22nm FinFET CMOS
Somnath Kundu, Likai Chai, Kailash Chandrashekar, Stefano Pellerano, Brent Carlton
Intel, Hillsboro, OR errors, which are compensated by the DTC-gain-correction loop. Each delay stage uses tristate inverter-based multiplexer (MUX) and switched capacitor banks to realize coarse and fine delays, respecti