ISSCC 2024

2024

222 篇论文 · AI / ML (33) · Power Management (30) · RF & Wireless (28) · Digital Processors (15)

ISSCC 2024 Session 16 Digital Processors
3nm Physical Unclonable Function with Multi-Mode Self-Destruction and 3.48×10-5 Bit Error Rate
Eric Hunt-Schroeder1, Parker Lin-Butler2, Amit Degada1, Tian Xia2
generate secure encryption keys by exploiting random and unpredictable variations in the manufacturing process. However, achieving an acceptably low Bit Error Rate (BER) below 1×10-4 remains a big challenge. Stable bit i
Marvell, Burlington, VT University of Vermont, Burlington, VT 1 2 Sili
ISSCC 2024 Session 16 Digital Processors
High-Density and Low-Power PUF Designs in 5nm Achieving 23× and 39× BER Reduction After Unstable Bit Detection and Masking
Sudhir Shrikantha Kudva1, Mahmut Ersin Sinangil1, Stephen Tell2,
Nikola Nedovic1, Sanquan Song1, Brian Zimmer1, C. Thomas Gray2 Nvidia, Santa Clara, CA Nvidia, Durham, NC 1 2 causes each inverter to have a slightly different VTC and the following stages are used to amplify the voltage
ISSCC 2024 Session 16 Digital Processors
A Synthesizable Design-Agnostic Timing Fault Injection Monitor Covering 2MHz to 1.26GHz Clocks in 65nm CMOS
Yan He, Kaiyuan Yang
Fault Injection Attacks (FIAs) are powerful attacks that induce and exploit faults in chips to create severe security consequences like faulty results, OS security bypass, and information leakage [1-3]. This paper focuse
Rice University, Houston, TX
ISSCC 2024 Session 16 Digital Processors
PACTOR: A Variation-Tolerant Probing-Attack Detector for a 2.5Gb/s×4-Channel Chip-to-Chip Interface in 28nm CMOS
Mao Li1, Zhaoqing Wang1, Sanu K. Mathew2, Vivek De2, Mingoo Seok1
Intel, Hillsboro, OR 1 2 A probing attack on PCB signal traces poses a substantial threat, as it provides an avenue for eavesdropping on transmitted data between chips. This technique can even be exploited for a complete
Columbia University, New York, NY
ISSCC 2024 Session 16 Digital Processors
Power and EM Side-Channel-Attack-Resilient AES-128 Core with Round-Aligned Globally-Synchronous-LocallyAsynchronous Operation Based on Tunable Replica Circuits random delay causes the availability of SMA outputs to downstream operations to be further temporally scattered within CLK boundary. The full 128b SMA output is never latched together due to all four TRCs being forced to have different random delays, recomputed every clock cycle.
Sirish Oruganti*1, Meizhi Wang*1, Vishnuvardhan V. Iyer1, Yipeng Wang1,
Mengtian Yang1, Raghavan Kumar2, Sanu K. Mathew2, Jaydeep P. Kulkarni1 While power and coarse-grained EM SCA target aggregated signatures, fine-grained EM SCA scans the chip and attacks specific activity regions. Combating
ISSCC 2024 Session 16 Digital Processors
A 60Mb/s TRNG with PVT-Variation-Tolerant Design Based on STR in 4nm
Jieun Park, Yong Ki Lee, Karpinskyy Bohdan, Yunhyeok Choi, Jonghoon Shin,
cryptographic algorithms, employing random numbers in a variety of cryptographic applications pursuing data integrity, confidentiality, and authenticity. They often require high-throughput capabilities for scenarios such
Hyo-Gyuem Rhew, Jongshin Shin Samsung Electronics, Hwaseong, Korea Tru
ISSCC 2024 Session 17 Other
Omnidirectional Magnetoelectric Power Transfer for Miniaturized Biomedical Implants via Active Echo
Wei Wang, Zhanghao Yu, Yiwei Zou, Joshua Woods, Prahalad Chari,
Jacob T. Robinson, Kaiyuan Yang Rice University, Houston, TX Wireless, batteryless, and miniaturized implants promise transformative therapies for various neurological, psychiatric, and cardiac disorders. Beyond conventi
ISSCC 2024 Session 17 Other
A 9mW Ultrasonic Through Transmission Transceiver for Non-Invasive Intracranial Pressure Sensing
Gerald Topalli1, Yingying Fan1, Matt Y. Cheung1, Ashok Veeraraghavan1,
(ICP) measures the pressure exerted by fluids and tissues inside the skull, typically 7-15mmHg for healthy adults. Conditions such as traumatic brain injury, hydrocephalus, and intracranial hemorrhage often cause elevated
Mohammad Hirzallah2, Taiyun Chi1 Rice University, Houston, TX Baylor C
ISSCC 2024 Session 17 Other
A Miniature Multi-Nuclei NMR/MRI Platform with a High-Voltage SOI ASIC Achieving a 134.4dB Image SNR with a 173×250×103µm3 Resolution
Shuhao Fan1, Qi Zhou1, Ka Meng LEI1, Rui P. Martins1,2, Pui-In Mak1
Instituto Superior Técnico/Universidade de Lisboa, Lisbon, Portugal 1 2 Magnetic resonance imaging (MRI), based on Nuclear Magnetic Resonance (NMR), is an indispensable tool for contemporary medicine. Moreover, the adven
University of Macau, Macau, China
ISSCC 2024 Session 17 Other
Environmentally-Friendly Disposable Circuit and Battery System for Reducing Impact of E-Wastes solution ((CH3COO)2Mg) with air (O2). Since a voltage of 10V or higher was required to operate the organic circuit, 12 series-connected cells were fabricated. This battery could maintain the voltage of more than 10V at a current of 100μA for more than 3 hours.
Naoki Miura*1, Hiroaki Taguchi*1, Kazuyoshi Watanabe2, Masaya Nohara1,
Tatsuyuki Makita3, Masahiro Tanabe3, Takahiro Wakimoto3, Shohei Kumagai2, Hideyuki Nosaka1, Atsushi Aratake1, Toshihiro Okamoto2, Shun Watanabe2, Jun Takeya2, Takeshi Komatsu1 The developed circuit and battery system was
ISSCC 2024 Session 17 Other
A 24V Mini-Coil Magnetic Neural Stimulator with Closed-Loop Deadtime Control and ZCS Control Achieving 99.76% Charge Recovery Efficiency to a short pulse PW1 by comparing it with the comparator’s reference voltage (VREF1). PW1 is then routed to the DT controller, which outputs EN1 and the rising edge of EN2. The falling edge of EN2 is generated by the second pulse generator followed by the ZCS controller.
Yingying Fan*, Yuxuan Liu*, Gerald Topalli, Roy Lycke, Lan Luan, Chong Xie, It’s worth noting that the time interval bet
of EN2 (i.e., DTEN) does not reflect the actual DT, due to the switching time of Q1-Q4 and Rice University, Houston, TX *Equally Credited Authors (ECAs) Neural stimulation has a variety of applications in neuroscience res
ISSCC 2024 Session 17 Other
Fully Integrated CMOS Ferrofluidic Biomolecular Processing
Platform with On-Chip Droplet-Based Manipulation, Multiplexing and Sensing
Dongwon Lee*1, Kyung-sik Choi*1, Fuze Jiang*1, Hangxing Liu1, Doohwan Jung2, Ying Kong1, Marco Saif1, Zhikai Huang1, Jing Wang1, Hua Wang1 ETH Zürich, Zurich, Switzerland Qualcomm, Santa Clara, CA *Equally Credited Autho
ISSCC 2024 Session 17 Other
Droplet Microfluidics Co-Designed with Real-Time CMOS Luminescence Sensing and Impedance Spectroscopy of 4nL Droplets at a 67mm/s Velocity
Qijun Liu, Diana Arguijo Mendoza, Alperen Yasar, Dilara Caygara, Aya Kassem,
cell-based biosensors (CBBs)
Douglas Densmore, Rabia Tugce Yazicigil Boston University, Boston, MA
ISSCC 2024 Session 17 Other
V 988nW Time-Domain Audio Feature Extraction for Keyword Spotting Using Injection-Locked Oscillators
Ali Mostafa, Emmanuel Hardy, Franck Badets
Always-on, voice-activated tinyML systems, like those implementing keyword spotting (KWS), demand low power consumption and a small footprint. In certain instances, subV energy-harvesting sources restrict the available s
CEA-Léti, Grenoble, France
ISSCC 2024 Session 18 RF & Wireless
A 600Gb/s DP-QAM64 Coherent Optical Transceiver Frontend with 4x105GS/s 8b ADC/DAC in 16nm CMOS
is symmetric from PLL to the four ADCs. In order to reduce jitter and random skew, it, uses only two stages of CMOS buff
clock channel of 1.2mm. The transmission line effect of the clock channel is carefully modeled to make sure the ADC clock has low jitter and low skew with sharp rail-to-rail edges. Guansheng Li1, Adesh Garg1, Tim He1, Ul
ISSCC 2024 Session 18 RF & Wireless
A 4×64Gb/s NRZ 1.3pJ/b Co-Packaged and Fiber-Terminated 4-Ch VCSEL-Based Optical Transmitter
Susnata Mondal, Junyi Qiu, Sashank Krishnamurthy, Joe Kennedy,
from limited reach due to channel loss. Multi-mode vertical-cavity surface-emitting laser (VCSEL)-based optical interconnects can enable high-bandwidth connectivity while extending the reach to tens of meters [1-3]. Plug
Soumya Bose, Tolga Acikalin, Shuhei Yamada, James Jaussi, Mozhgan Mans
ISSCC 2024 Session 18 RF & Wireless
An 8b 160GS/s 57GHz Bandwidth Time-Interleaved DAC and Driver-Based Transmitter with Adaptive Calibration for 800Gb/s Coherent Optical Applications in 5nm
periods (Ts and 2Ts). This duty cycle target estimation is common for all the slices, considering that slice-to-slice tr
eq (1) F. Ahmad1, A. Mellati1, A. Fernandez2, A. Iyer 3, A. Fan1, B. Reyes 2, C. Abidin 1, C. Nani 4, D. Albano 4, F. Solis 2, G. Minoia 4, G. Hatcher 1, H. Carrer 2, K. Kota 1, L. Wang 1, M. Bachu 3, M. Garampazzi 4, M.
ISSCC 2024 Session 18 RF & Wireless
A 200GS/s 8b 20fJ/c-s Receiver with >60GHz AFE Bandwidth for 800Gb/s Optical Coherent Communications in 5nm FinFET
R. L. Nguyen1, A. Mellati1, A. Fernandez2, A. Iyer3, A. Fan1, B. Reyes2, C. Abidin1,
C. Nani4, D. Albano4, F. Ahmad1, F. Solis2, G. Minoia4, G. Hatcher1, M. Bachu3, M. Garampazzi4, M. Hassanpourghadi1, N. Fan1, P. Prabha1, S. Fan3, S. Ho5, T. Dusatko5, T. Wu1, W. Elsharkasy1, Z. Sun6, S. Jantzi1, L. Tse3
ISSCC 2024 Session 19 RF & Wireless
A 7.5GHz Subharmonic Injection-Locked Clock Multiplier with
a 62.5MHz Reference, -259.7dB FoMJ, and -56.6dBc Reference, Spur
multipliers, as it can lower the phase noise of a VCO beyond what can be achieved by the PLL loop bandwidth. The amount of phase-noise reduction depends on the injection strength and reaches a maximum when the clock edge
Hangil Choi, SeongHwan Cho Korea Advanced Institute of Science and Tec
ISSCC 2024 Session 19 RF & Wireless
An 8.9-to-21.9GHz Single-Core Oscillator with Reconfigurable Class-F-1 and Enhanced-Colpitts Dual-Mode Operation Achieving 209dBc/Hz FoMT
Zehui Kang, Chen Yu, Liang Wu
Emerging needs for incorporating multistandard or software-defined-radio transceivers onto a single chip necessitate oscillator signals with an octave coverage for enabling seamless full-range frequency synthesis. Althoug
Chinese University of Hong Kong, Shenzhen, China
ISSCC 2024 Session 19 RF & Wireless
A 0.07mm2 20-to-23.8GHz 8-phase Oscillator Incorporating Magnetic + Dual-Injection Coupling Achieving 189.2dBc/Hz FoM@10MHz and 200.7dBc/Hz FoMA in 65nm CMOS
Ya Zhao*1, Chao Fan*1, Qiuyu Fang1, Guohe Zhang1, Jun Yin2, Pui-in Mak2, Li Geng1
low phase noise (PN) and low phase errors are the cornerstone of high-data-rate wireless transceivers, especially with the increasingly more complex modulation schemes. Frequency division, polyphase filters, and ring osci
Xi’an JiaoTong University, Xi’an, China University of Macau, Macao, Ch
ISSCC 2024 Session 19 RF & Wireless
A 13.7-to-41.5GHz 214.1dBc/Hz FoMT Quad-Core Quad-Mode VCO Using an Oscillation-Mode-Splitting Technique
Huanyu Ge, Haikun Jia, Wei Deng, Ruichang Ma, Zhihua Wang, Baoyong Chi
Voltage-controlled-oscillators (VCOs) with simultaneous low phase noise and wide frequency tuning range (FTR) spanning from tens GHz to millimeter-wave (mm-wave) bands are required for various standardized applications,
Tsinghua University, Beijing, China
ISSCC 2024 Session 2 Digital Processors
A 4nm 3.4GHz Tri-Gear Fully Out-of-Order ARMv9.2 CPU Subsystem-Based 5G Mobile SoC
Anshul Varma1, Sumanth Gururajarao1, HsinChen Chen1, Tao Chen1,
Gordon Gammie1, Hugh Mair2, Jen-Hang Yang3, Hao-Hsiang Yu3, Shun-Chieh Chang3, Cheng-Hao Yang3, Li-An Huang3, Kumar Ramanathan1, Ramesh Halli4, Efron Ho1, Ta-Wen Hung3, Sung S.-Y. Hsueh3, LiangChe Li3, Achuta Thippana1,
ISSCC 2024 Session 2 Digital Processors
“Zen 4c”: The AMD 5nm Area-Optimized x86-64 Microprocessor Core
These area optimizations resulted in a “Zen 4c” core, including the L2 cache, that was, 35% smaller than the “Zen 4” cor
3.84mm2. Side-by-side images shown in Fig. 2.2.3. To fit two CCXs onto one chiplet die, the L3 cache in one CCX was reduced from 32MB to 16MB. The extra frequency margin also allowed pairs of L3 data macros to be combined
ISSCC 2024 Session 2 Digital Processors
Emerald Rapids: 5th-Generation Intel® Xeon® Scalable Processors
Ashley O. Munch1, Nevine Nassif1, Carleton L. Molnar1, Jason Crop2,
Rich Gammack1, Chinmay P. Joshi3, Goran Zelic1, Kambiz Munshi1, Min Huang4, Charles R. Morganti2, Sireesha Kandula1, Arijit Biswas1 Intel, Hudson, MA 2 Intel, Fort Collins, CO 3 Intel, Hillsboro, OR 4 Intel, Santa Clara,
ISSCC 2024 Session 2 Digital Processors
ATOMUS: A 5nm 32TFLOPS/128TOPS ML System-on-Chip for Latency Critical Applications
Chang-Hyo Yu, Hyo-Eun Kim, Sungho Shin, Kyeongryeol Bong, Hyunsuk Kim,
Yoonho Boo, Jaewan Bae, Minjae Kwon, Karim Charfi, Jinseok Kim, Hongyun Kim, Myeongbo Shim, Changsoo Ha, Wongyu Shin, Jae-Sung Yoon, Miock Chi, Byungjae Lee, Sungpill Choi, Donghan Kim, Jeongseok Woo, Seokju Yoon, Hyunje
ISSCC 2024 Session 2 Digital Processors
A 28nm Physical-Based Ray-Tracing Rendering Processor for Photorealistic Augmented Reality with Inverse Rendering and Background Clustering for Mobile Devices
Shiyu Guo1, Sachin Sapatnekar2, Jie Gu1
University of Minnesota, Minneapolis, MN includes a sub-group of user-defined objects inside. After the BBOX Intersection Evaluator (BBIE) detects intersection with TBBOX, the Triangle Mesh Intersection Evaluator (TIE) co
Northwestern University, Evanston, IL
ISSCC 2024 Session 2 Digital Processors
A 131mW 6.4Gbps 256×32 Multi-User MIMO OTFS Detector for Next-Gen Communication Systems unit computes the soft information by piece-wise linear functions. The channel memory bank includes one channel-sample memory and one channel-difference memory for storing the encoded Gram matrix coefficients.
Tang Lee, Ting-Yang Chen, I-Hsuan Liu, Chia-Hsiang Yang, Figure 2.6.4 shows the detailed architecture and optimization t
The mean values are computed along the diagonal band of the submatrix in a block-byblock manner. It is noted that the mean values for the lower-left and upper-right blocks can be derived from the symbols updated in the p
ISSCC 2024 Session 2 Digital Processors
BayesBB: A 9.6Gbps 1.61ms Configurable All-MessagePassing Baseband-Accelerator for B5G/6G Cell-Free Massive-MIMO in 40nm CMOS
Yi Zhang*1,2, Wenyue Zhou*1,2, Yiwei Zhang1,2, Houren Ji1,2, Yongming Huang1,2,
7.4 illustrates the implementation details of the MIMO-BP detector, utilizing a fully unfolded architecture with 5 iterations. The Gaussian approximation of interference is first measured to support the posterior message
Xiaohu You1,2, Chuan Zhang1,2 Southeast University, Nanjing, China Pur
ISSCC 2024 Session 20 AI / ML
NVE: A 3nm 23.2TOPS/W 12b-Digital-CIM-Based Neural Engine for High-Resolution Visual-Quality Enhancement on Smart Devices
Ming-En Shih*1, Shih-Wei Hsieh*1, Ping-Yuan Tsai*1, Ming-Hung Lin1,
Pei-Kuei Tsung1, En-Jui Chang1, Jenwei Liang1, Shu-Hsin Chang1, Chung-Lun Huang1, You-Yu Nian1, Zhe Wan2, Sushil Kumar2, Cheng-Xin Xue1, Gajanan Jedhe2, Hidehiro Fujiwara3, Haruki Mori3, Chih-Wei Chen1, Po-Hua Huang1, Ch
ISSCC 2024 Session 20 AI / ML
A 28nm 74.34TFLOPS/W BF16 Heterogenous CIM-Based Accelerator Exploiting Denoising-Similarity for Diffusion Models
Ruiqi Guo1, Lei Wang1, Xiaofeng Chen1, Hao Sun1, Zhiheng Yue1, Yubin Qin1,
China 3 Shanghai AI Lab, Shanghai, China 1 2 Diffusion models (DMs) have emerged as a powerful category of generative models with record-breaking performance in image synthesis [1]. A noisy image created from pure Gaussi
Huiming Han1, Yang Wang1, Fengbin Tu2, Shaojun Wei1, Yang Hu1, Shouyi
ISSCC 2024 Session 20 AI / ML
A 23.9TOPS/W @ 0.8V, 130TOPS AI Accelerator with 16× Performance-Accelerable Pruning in 14nm Heterogeneous Embedded MPU for Real-Time Robot Applications
Koichi Nose, Taro Fujii, Katsumi Togawa, Shunsuke Okumura, Kentaro Mikami,
expectations for the advancement of human-cooperative robots. In such robots, advanced environmental recognition (mainly AI based), planning and control (normally non-AI algorithms) have to be processed simultaneously in
Daichi Hayashi, Teruhito Tanaka, Takao Toi Renesas Electronics, Tokyo,
ISSCC 2024 Session 20 AI / ML
A 28nm Physics Computing Unit Supporting Emerging Physics-Informed Neural Network and Finite Element Method for Real-Time Scientific Computing on Edge Devices
Yuhao Ju, Ganqi Xu, Jie Gu
The demand for real-time computing on edge devices from emerging applications, e.g. AI, has exploded in recent years. Lately, physics-based scientific computing has also drawn significant interests driven by the growth of
Northwestern University, Evanston, IL
ISSCC 2024 Session 20 AI / ML
C-Transformer: A 2.6-18.1μJ/Token Homogeneous DNN-Transformer/Spiking-Transformer Processor with Big-Little Network and Implicit Weight Generation for Large Language Models
Sangyeob Kim, Sangjin Kim, Wooyoung Jo, Soyeon Kim, Seongyon Hong, Hoi-Jun Yoo
20.5.1, are widely used, and even on-device LLM systems with real-time responses are anticipated
Korea Advanced Institute of Science and Technology, Daejeon, Korea Rec
ISSCC 2024 Session 20 AI / ML
LSPU: A Fully Integrated Real-Time LiDAR-SLAM SoC with Point-Neural-Network Segmentation and Multi-Level kNN Acceleration
Jueun Jung1, Seungbin Kim1, Bokyoung Seo1, Wuyoung Jang1, Sangho Lee1,
mobile robots require Simultaneous Localization and Mapping (SLAM) for autonomous driving and seamless interaction with the surrounding objects. Previous RGB-based visual SLAM processors [1-2] cannot be deployed for auto
Jeongmin Shin1, Donghyeon Han2, Kyuho Jason Lee1 Ulsan National Instit
ISSCC 2024 Session 20 AI / ML
NeuGPU: A 18.5mJ/Iter Neural-Graphics Processing Unit for Instant-Modeling and Real-Time Rendering with SegmentedHashing Architecture
Junha Ryu1, Hankyul Kwon1, Wonhoon Park1, Zhiyong Li1, Beomseok Kwon1,
Cambridge, MA 1 2 With the rise of the metaverse, there’s a growing demand for 3D modeling and rendering technologies that can bring real-world objects/scenes into the augmented/virtual world on mobile devices. Recently,
Donghyeon Han2, Dongseok Im1, Sangyeob Kim1, Hyungnam Joo1, Hoi-Jun Yo
ISSCC 2024 Session 20 AI / ML
Space-Mate: A 303.5mW Real-Time Sparse Mixture-ofExperts-Based NeRF-SLAM Processor for Mobile Spatial Computing
Gwangtae Park1, Seokchan Song1, Haoyang Sang1, Dongseok Im1,
Recently, spatial computing has become popular in mobile devices, such as autonomous robots and augmented reality (AR) glasses [1], and it enables cyber-physical interaction through accurate user position and 3D geometri
Donghyeon Han2, Sangyeob Kim1, Hongseok Lee1, Hoi-Jun Yoo1 Korea Advan
ISSCC 2024 Session 21 Other
A 121.7dB DR and -109.0dB THD+N Filterless Digital-Input Class-D Amplifier with an HV Multibit IDAC Using Tri-level Output and Employing a Transition-Rate-Balanced Bidirectional RTDEM Scheme
Huajun Zhang*1, Mingshuang Zhang*1, Mengying Chen1, Arthur Admiraal1,
Digital-input Class-D amplifiers (CDAs) are widely used in audio applications and offer high power efficiency and high levels of integration. As human ears have a dynamic range (DR) of ~130dB, high DR is preferred in high-
Miao Zhang1, Marco Berkhout2, Qinwen Fan1 Delft University of Technolo
ISSCC 2024 Session 21 Other
A -106.3dB THD+N Feedback-After-LC Class-D Audio Amplifier Employing Current Feedback to Enable 530kHz LC-Filter Cut-Off Frequency
Huajun Zhang1, Haochun Fan1, Miao Zhang1, Marco Berkhout2, Qinwen Fan1
Goodix Technology, Nijmegen, The Netherlands 1 2 Class-D amplifiers (CDAs) are used in various audio applications thanks to their high power efficiency. However, they produce high-frequency switching energy that poses EMI
Delft University of Technology, Delft, The Netherlands
ISSCC 2024 Session 22 Analog Circuits
A 12GS/s 12b 4× Time-Interleaved Pipelined ADC with Comprehensive Calibration of TI Errors and Linearized Input Buffer
Yuefeng Cao1, Minglei Zhang1, Yan Zhu1, R. P. Martins1,2, Chi-Hang Chan1
Instituto Superior Tecnico/University of Lisboa, Lisbon, Portugal 1 2 Direct RF sampling relieves the analog front-end design and delivers high system flexibility. In >10GS/s >10b ADCs, time-interleaving (TI) is inescapab
University of Macau, Macau, China
ISSCC 2024 Session 22 Analog Circuits
A 700MHz-BW –164dBFS/Hz-Small-Signal-NSD 703mW Continuous-Time Pipelined ADC with On-Chip Digital Reconstruction Achieving <-85dBFS HD3 using Digital Cancellation of DAC Errors The 2nd stage’s (Fig. 22.2.2) relaxed NSD allows a low-area RC lattice delay and a PMOSonly current-steering sub-DAC without negative supplies. The flash sub-ADC is identical to the one in the 1st stage, while the interstage filter is an impedance-scaled version of its 1st-stage counterpart. The 3rd stage is a VCO ADC with a V-to-I converter and a phaseinterpolated ring oscillator with over-range and nonlinearity corrections [3].
Sharvil Patil1, Asha Ganesan1, Hajime Shibata1, Victor Kozlov1, Gerry Taylor2,
Qingnan Yu3, Zhao Li1, Zeynep Lulec1, Konstantinos Vasilakopoulos1, Prawal Shrestha2, Donald Paterson4, Raviteja Theertham1, Aseer Chowdhury5 The DRF (Fig. 22.2.1) combines stage outputs such that sub-ADC quantization er
ISSCC 2024 Session 22 Analog Circuits
A 76mW 40GS/s 7b Time-Interleaved Hybrid Voltage/TimeDomain ADC with Common-Mode Input Tracking
Amy Whitcombe1, Somnath Kundu2,4, Hariprasad Chandrakumar2,
Hillsboro, OR 1 2 Fast, low-power ADCs with ~5-6 effective bits of resolution are a key element of 50+Gb/s links, which often use DSP-based equalization to compensate for high channel loss and high-order modulation schem
Abhishek Agrawal2, Thomas Brown2, Steven Callender3, Brent Carlton2, S
ISSCC 2024 Session 22 Analog Circuits
A 4.8GS/s 7-ENoB Time-Interleaved SAR ADC with Dither-Based Background Timing-Skew Calibration and Bit-Distribution-Based Background Ping-Pong Comparator Offset Calibration
Yunsong Tao, Mingyang Gu, Baoyong Chi, Yi Zhong, Lu Jie, Nan Sun
High-speed (>GS/s) medium-resolution (6-8b) ADCs are in high demand for wideband applications. The time-interleaved (TI) SAR ADC is widely used for its superior power efficiency. However, TI ADCs suffer from timing-skew m
Tsinghua University, Beijing, China
ISSCC 2024 Session 22 Analog Circuits
A 42GS/s 7b 16nm Massively Time-Interleaved Slope-ADC
Ewout Martens1, Adam Cooman1, Pratap Renukaswamy1, Shun Nagata2,
resolution of 6 to 8 bits and a sampling speed of several tens of GHz are often required [1–5]. To achieve these extremely high speeds, time-interleaved (TI) ADCs with tens of parallel high-speed channels are commonly us
Sehoon Park1, Jorge Lagos1, Nereo Markulic1, Jan Craninckx1 1 2 imec,
ISSCC 2024 Session 23 Other
A 44μW IoT Tag Enabling 1μs Synchronization Accuracy and OFDMA Concurrent Communication with Software-Defined Modulation
Jiaqi Shen*1, Fengyuan Zhu*2, Yang Liu1, Boxiao Liu1, Chunqi Shi1,
2 Backscatter tags have proven advantageous in reducing the power consumption of ultralow upload data-rate IoT devices from milliwatts to tens of microwatts [1,2]. Previous backscatter ICs generally employ codeword trans
Leilei Huang1, Long Xu1, Xiaohua Tian2, Runxi Zhang1 East China Normal
ISSCC 2024 Session 23 Other
A 1mm2 Software-Defined Dual-Mode Bluetooth Transceiver with 10dBm Maximum TX Power and -98.2dBm Sensitivity 2.96mW RX Power at 1Mb/s
Nicola Scolari, Franz X. Pengg, Konstantinos Manetakis, Camilo A. Salazar,
Alexandre Vouilloz, Ernesto Pérez Serna, Anjana Dissanayake, Pascal Persechini, Vladimir Kopta, Erwan Le Roux, Francesco Chicco, Stefano Cillo, Nicola Gerber, Cédric Barbelenet, Fabio Epifano, Paulo A. Dal Fabbro, Nicola
ISSCC 2024 Session 23 Other
A Passive Crystal-Less Wi-Fi-to-BLE Tag Demonstrating Battery-Free FDD Communication with Smartphones
Ziyi Chang*1, Qijing Xiao*1, Cheng Chen2, Weixiao Wang1, Xin Hu1,
of Things (IoT) applications become increasingly widespread, wireless connectivity presents stringent requirements on low power, low cost, and compatibility with widely deployed commodity hardware such as BLE/Wi-Fi-embed
Changgui Yang1, Zhuhao Li1, Yuxuan Luo1, Bo Zhao1 Zhejiang University,
ISSCC 2024 Session 23 Other
A 167μW 71.7dB-SFDR 2.4GHz BLE Receiver Using a Passive
Quadrature-Front-End, a Double-Sided Double-Balanced, Cascaded Mixer and a Dual-Transformer-Coupled Class-D VCO
Haijun Shao1, Rui P. Martins1,2, Pui-In Mak1 University of Macau, Macau, China University of Lisboa, Lisboa, Portugal 1 2 The Bluetooth Low-Energy (BLE) receivers evolved from their traditional active RF frontends [1,2]
ISSCC 2024 Session 23 Other
A 7.6mW IR-UWB Receiver Achieving -13dBm Blocker Resilience with a Linear RF Front-End
Anoop Narayan Bhat, Paul Mateman, Zule Xu, Peter Vis, Paul Detterer,
Gururaja Kasanadi Ramachandra, Yunus Baykal, Mario Konijnenburg, Yao-Hong Liu, Christian Bachmann, Peng Zhang imec, Eindhoven, The Netherlands 802.15.4a/z enabled IR-UWB TRXs [1-4] are being widely deployed into secured
ISSCC 2024 Session 25 Other
Short-Reach Silicon Photonic Interconnects with Quantum Dot Mode Locked Laser Comb Sources
Andrew Netherton1, Mario Dumont1, Zachary Nelson1, Jinesh Jhonsa1,
Alice Mo1, Jahyun Koo1, David McCarthy1, Noah Pestana2, Skylar Deckoff-Jones2, Christopher Poulton2, Michael Frankel3, Jock Bovington4, Luke Theogarajan1, John Bowers1 University of California, Santa Barbara, CA Analog P