ISSCC 2019
Session 5
Image Sensors
A 256×256 40nm/90nm CMOS 3D-Stacked 120dBDynamic-Range Reconfigurable Time-Resolved SPAD Imager
Kingdom 3 Heriot-Watt University, Edinburgh, United Kingdom 1 2 Light Detection and Ranging (LIDAR) applications pose extremely challenging dynamic range (DR) requirements on optical time-of-flight (ToF) receivers due to
ISSCC 2019
Session 5
Image Sensors
A 32×32-Pixel 0.9THz Imager with Pixel-Parallel 12b VCO-Based ADC in 0.18μm CMOS
characteristics of signals in the terahertz band (100GHz to 10THz) located between the millimeter wave band and the infrared band. In particular, terahertz waves have higher spatial resolution than mm-waves. Moreover, th
ISSCC 2019
Session 6
Wireline I/O
A 100Gb/s 1.1pJ/b PAM-4 RX with Dual-Mode 1-Tap PAM4 / 3-Tap NRZ Speculative DFE in 14nm CMOS FinFET
wireline communications has led to emerging standards in the 100Gb/s+ range using PAM-4 signaling. ADC-based receivers have demonstrated robust operation over channels with high losses (>20dB) [1], but their power consum
ISSCC 2019
Session 6
Wireline I/O
A 60Gb/s PAM-4 ADC-DSP Transceiver in 7nm CMOS with SNR-Based Adaptive Power Scaling Achieving 6.9pJ/b at 32dB Loss
Semyon Lebedev, Petar Krotnev, Dorin Alexandru Nicolescu, Dmitry Petrov, Carlos Carvalho, Stephen Alie, Euhan Chong, Faisal Ahmed Musa, Davide Tonietto Huawei Technologies, Ottawa, ON, Canada With the introduction of PAM
ISSCC 2019
Session 6
Wireline I/O
A Sub-250mW 1-to-56Gb/s Continuous-Range PAM-4 42.5dB IL ADC/DAC-Based Transceiver in 7nm FinFET
Marco Sosio, Enrico Pozzati, Nicola Ghittori, Federico Magni, Marco Garampazzi, Giacomino Bollati, Antonio Milani, Alberto Minuti, Fabio Giunco, Paola Uggetti, Ivan Fabiano, Nicola Codega, Alessandro Bosi, Nicola Carta,
ISSCC 2019
Session 6
Wireline I/O
A 180mW 56Gb/s DSP-Based Transceiver for HighDensity IOs in Data Center Switches in 7nm FinFET Technology
Po-Shuan Weng2, Yi-Chieh Huang2, Chun-Cheng Liu2, Chien-Hua Wu2, Shih-Hao Huang2, Chungshi Lin2, Ke-Chung Wu2, Kun-Hung Tsai2, Kai-Wen Tan2, Ahmed ElShater1, Kuang-Ren Chen2, Wei-Hao Tsai2, Huan-Sheng Chen2, Weiyu Leng1,
ISSCC 2019
Session 6
Wireline I/O
A 400Gb/s Transceiver for PAM-4 Optical Direct-Detect Application in 16nm FinFET
F. Rad3, J. Riani3, J. Pernillo3, J. Sun1, J. Wong3, K. Abdelhalim2, K. Gopalakrishnan3, K. Kim2, L. Tse3, M. Davoodi2, M. Le2, M. Zhang3, M. Talegaonkar2, P. Prabha2, R. Mohanavelu3, S. Chong1, S. Forey4, S. Netto3, S.
ISSCC 2019
Session 6
Wireline I/O
A 128Gb/s 1.3pJ/b PAM-4 Transmitter with Reconfigurable 3-Tap FFE in 14nm CMOS
Herschel A. Ainspan, Timothy O. Dickson, Michael P. Beakes, Mounir Meghelli IBM T. J. Watson Research Center, Yorktown Heights, NY The ever-increasing demand for higher bandwidth continues to fuel the need for faster and
ISSCC 2019
Session 6
Wireline I/O
A 112Gb/s PAM-4 Voltage-Mode Transmitter with 4-Tap Two-Step FFE and Automatic Phase Alignment Techniques in 40nm CMOS
transmitters to operate at higher speeds. The applications of 400GbE also push the transmitter to be designed at 112Gb/s for a single lane [1-2]. However, the use of advanced processes (<16nm) hardly reduces the costs. T
ISSCC 2019
Session 6
Wireline I/O
A 36Gb/s Adaptive Baud-Rate CDR with CTLE and 1-Tap DFE in 28nm CMOS
circuits (CDR) are ubiquitous in recent receiver designs as a means of lowering power consumption by sampling the data only once per UI. To further reduce power, prior works in pattern-based baud-rate PD
ISSCC 2019
Session 7
AI / ML
An 11.5TOPS/W 1024-MAC Butterfly Structure Dual-Core Sparsity-Aware Neural Processing Unit in 8nm Flagship Mobile SoC
widely applied for image and speech recognition. Response time, connectivity, privacy and security drive applications towards mobile platforms rather than cloud. For mobile systems-on-a-chip (SoCs), energyefficient neural
ISSCC 2019
Session 7
AI / ML
A 20.5TOPS and 217.3GOPS/mm2 Multicore SoC with DNN Accelerator and Image Signal Processor Complying with ISO26262 for Automotive Applications
Soichiro Hosoda, Fumihiko Hyuga, Akira Moriya, Ryuji Hada, Atsushi Masuda, Masato Uchiyama, Tomohiro Koizumi, Takanori Tamai, Nobuhiro Sato, Jun Tanabe, Katsuyuki Kimura, Ryusuke Murakami, Takashi Yoshikawa Toshiba Elect
ISSCC 2019
Session 7
AI / ML
An 879GOPS 243mW 80fps VGA Fully Visual CNN-SLAM Processor for Wide-Range Autonomous Exploration
University of Michigan, Ann Arbor, MI Simultaneous localization and mapping (SLAM) estimates an agent’s trajectory for all six degrees of freedom (6 DoF) and constructs a 3D map of an unknown surrounding. It is a fundame
ISSCC 2019
Session 7
AI / ML
A 2.1TFLOPS/W Mobile Deep RL Accelerator with Transposable PE Array and Experience Compression
but also for action control, so that an autonomous system, such as the robot, can perform human-like behaviors and operations. Unlike recognition tasks, real-time operation is important in action control, and it is too s
ISSCC 2019
Session 7
AI / ML
A 65nm 0.39-to-140.3TOPS/W 1-to-12b Unified NeuralNetwork Processor Using Block-Circulant-Enabled Transpose-Domain Acceleration with 8.1× Higher TOPS/mm2 and 6T HBST-TRAM-Based 2D Data-Reuse Architecture
Yung-Ning Tu2, Yi-Ju Chen2, Ao Ren3, Yanzhi Wang3, Meng-Fan Chang2, Xueqing Li1, Huazhong Yang1, Yongpan Liu1 Tsinghua University, Beijing, China National Tsing Hua University, Hsinchu, Taiwan 3 Northeastern University,
ISSCC 2019
Session 7
AI / ML
A 65nm 236.5nJ/Classification Neuromorphic Processor with 7.5% Energy Overhead On-Chip Learning Using Direct Spike-Only Feedback
classifying handwritten digits, the learning rule can be directly adopted in general fully-connected networks with different network structures and hence can be extended to other applications. For example, the algorithm
ISSCC 2019
Session 7
AI / ML
LNPU: A 25.3TFLOPS/W Sparse Deep-Neural-Network Learning Processor with Fine-Grained Mixed Precision of FP8-FP16
for energy-efficient deep learning (DL) acceleration [1-6]. Most prior DNN inference accelerators are trained in the cloud using public datasets; parameters are then downloaded to implement AI [1-5]. However, local DNN le
ISSCC 2019
Session 8
Power Management
A Continuous-Input-Current Passive-Stacked Third-Order Buck Converter Achieving 0.7W/mm2 Power Density and 94% Peak Efficiency
The power density and efficiency of power-management integrated circuits (PMICs) is playing an increasingly important role in the miniaturization of modern computing platforms. Small inductors can be used to help miniatur
ISSCC 2019
Session 8
Power Management
A 10.9W 93.4%-Efficient (27W 97%-Efficient) FlyingInductor Hybrid DC-DC Converter Suitable for 1-Cell (2-Cell) Battery Charging Applications
The annual increase in performance and feature density of mobile products has driven the need for batteries with higher capacity and thus higher power-delivery solutions to maintain sensible charging times. The USB-C pow
ISSCC 2019
Session 8
Power Management
Fully Integrated Buck Converter with 78% Efficiency at 365mW Output Power Enabled by Switched-InductorCapacitor Topology and Inductor Current Reduction Technique
power consumption of system-on-chip by providing point-of-load regulation with dynamic voltage scaling [1]. As a core component of a buck converter, an inductor with large inductance and small resistance is desirable for
ISSCC 2019
Session 8
Power Management
A Fully Integrated Voltage Regulator in 14nm CMOS with
Christopher Schaef1, Nachiket Desai1, Harish Krishnamurthy1, Sheldon Weng1, Huong Do2, William Lambert2, Kaladhar Radhakrishnan2, Krishnan Ravichandran1, James Tschanz1, Vivek De1 Intel, Hillsboro, OR Intel, Chandler, AZ
ISSCC 2019
Session 8
Power Management
A Fully Integrated 85%-Peak-Efficiency Hybrid MultiRatio Resonant DC-DC Converter with 3.0-to-4.5V Input and 500µA-to-120mA Load Range by a fast capacitive level shifter, which results in very energy efficient highfrequency signal shifting. In contrast, pulsed cascode level shifters are used for
static losses compared to the fast dynamic level shifters. Peter Renz1, Maik Kaufmann1, Michael Lueders2, Bernhard Wicht1 Leibniz University Hannover, Hannover, Germany 2 Texas Instruments, Freising, Germany 1 DC-DC conv
ISSCC 2019
Session 8
Power Management
A 2MHz 4-to-60VIN Buck-Boost Converter for Automotive Use Achieving 95% Efficiency and CISPR 25 Class 5 Standard
High-voltage highly efficient switching power converters have gained high popularity in automotive applications. Powered by the car battery (VIN), the converters need to experience a wide VIN range from 4V to 60V under ha
ISSCC 2019
Session 9
mm-Wave
Toward Automotive Surround-View Radars
Weishow Hsu1, Jing-Hong Conan Zhan1, Brian Juan1, Chi-Hang Lok1, Sam Lee1, PC Hsiao1, Qiang Zhou2, Mark Wei1, Hsiang-Yun Chu1, Yu-Lun Chen1, Chao-Ching Hung1, Kevin Fong1, Po-Chun Huang1, Pierce Chen1, Sheng-Yuan Su1, Ya
ISSCC 2019
Session 9
mm-Wave
A 192-Virtual-Receiver 77/79GHz GMSK Code-Domain MIMO Radar System-on-Chip
Lysander Lim, Ryan Lobo, Dave Welland, Chung-Kai Chow, Andrew Dornbusch, Tim Dupuis, Struan Vaz, Fred Rush, Paul Bassett, Hong Kim, Monier Maher, Otto Schmid, Curtis Davis, Manju Hegde Uhnder, Austin, TX MIMO radars tran
ISSCC 2019
Session 9
mm-Wave
A 680µW Burst-Chirp UWB Radar Transceiver for Vital Signs and Occupancy Sensing up to 15m Distance
Johan Dijkhuis1, Wilfried Zomagboguelou1,3, Arjan Breeschoten1, Stefano Traferro1, Yan Zhan1, Tom Torf4, Christian Bachmann1, Pieter Harpe3, Masoud Babaie2 imec - Netherlands, Eindhoven, The Netherlands Delft University
ISSCC 2019
Session 9
mm-Wave
A 145GHz FMCW-Radar Transceiver in 28nm CMOS
require a high range resolution. This paper presents a 145GHz FMCW radar transceiver with on-chip antennas in 28nm bulk CMOS. An RF bandwidth of 13GHz yields an 11mm range resolution, and the high RF carrier permits grea
ISSCC 2019
Session 9
mm-Wave
An 80Gb/s 300GHz-Band Single-Chip CMOS Transceiver
Technology, Koganei, Japan 3 Panasonic, Yokohama, Japan 1 2 IEEE Standard 802.15.3d, published in October 2017, defines a high-data-rate wireless physical layer that enables up to 100Gb/s using the lower THz frequency ran
ISSCC 2019
Session 9
mm-Wave
A 42.2Gb/s 4.3pJ/b 60GHz Digital Transmitter with 12b/Symbol Polarization MIMO
in modern-day handheld computing devices around the unlicensed 57-to-71GHz band, the IEEE 802.11ay standard [1] supports 2-to-4× bonding of 2.16GHz channels (i.e. 4.32 to 8.64GHz), constellations up to 64QAM, and spatial
ISSCC 2019
Session 9
mm-Wave
A Scalable 71-to-76GHz 64-Element Phased-Array Transceiver Module with 2×2 Direct-Conversion IC in 22nm FinFET CMOS Technology
Somnath Kundu1, Abhishek Agrawal1, Peter Sagazio1, Brent Carlton1, Farhana Sheikh1, Arnaud Amadjikpe1, William Lambert3, Divya Shree Vemparala1, Mark Chakravorti1, Satoshi Suzuki1, Robert Flory1, Chris Hull1 Intel, Hills
ISSCC 2019
Session 9
mm-Wave
A 28GHz 20.3%-Transmitter-Efficiency 1.5°-Phase-Error Beamforming Front-End IC with Embedded Switches and Dual-Vector Variable-Gain Phase Shifters
Hanbat National University, Daejeon, Korea *Equally-Credited Authors (ECAs) 1 respectively. The NF of RX at 28GHz is 4.58dB, which is increased only by 1dB compared to simulated NF of LNA without switch and PA. NF variat
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