ISSCC 2023

2023

200 篇论文 · AI / ML (28) · Power Management (24) · RF & Wireless (20) · Data Converters (15)

ISSCC 2023 Session 32 AI / ML
SciCNN: A 0-Shot-Retraining Patient-Independent Epilepsy-Tracking SoC
Chne-Wuen Tsai1,2, Rucheng Jiang1, Lian Zhang1,3, Miaolin Zhang1,4, Liuhao Wu1,
Institute for Health, Singapore, Singapore 3 Apple, Cupertino, CA 4 Huawei Technologies, Chengdu, China 1 2 Patient-specific seizure-detection SoCs targeting ambulatory seizure treatment [1-8] achieve outstanding accurac
Jiaqi Guo1, Zhongwei Yan1, Jerald Yoo1,2 National University of Singap
ISSCC 2023 Session 32 Medical & Bio
Fascicle-Selective Bidirectional Peripheral Nerve Interface IC with 173dB FOM Noise-Shaping SAR ADCs and 1.38pJ/b Frequency-Multiplying Current-Ripple Radio Transmitter
Jianxiong Xu, José Sales Filho, Sudip Nag, Liam Long, Camilo Tejeiro,
Eugene Hwang, Gerard O’Leary, Yu Huang, Mustafa Kanchwala, Mohammad Abdolrazzaghi, Chenxi Tang, Patty Liu, Yuan Sui, Xilin Liu, George Eleftheriades, José Zariffa, Roman Genov University of Toronto, Toronto, Canada The p
ISSCC 2023 Session 33 AI / ML
A 16nm 32Mb Embedded STT-MRAM with a 6ns Read-Access
Time, a 1M-Cycle Write Endurance, 20-Year Retention at, 150°C and MTJ-OTP Solutions for Magnetic Immunity
Po-Hao Lee, Chia-Fu Lee, Yi-Chun Shih, Hon-Jarn Lin, Yen-An Chang, Cheng-Han Lu, Yu-Lin Chen, Chieh-Pu Lo, Chung-Chieh Chen, Cheng-Hsiung Kuo, Tan-Li Chou, Chia-Yu Wang, J. J. Wu, Roger Wang, Harry Chuang, Yih Wang, Yu-D
ISSCC 2023 Session 33 AI / ML
A 22nm 8Mb STT-MRAM Near-Memory-Computing Macro with 8b-Precision and 46.4-160.1TOPS/W for Edge-AI Devices
Yen-Cheng Chiu*1, Win-San Khwa*2, Chung-Yuan Li1, Fang-Ling Hsieh1,
Yu-An Chien1, Guan-Yi Lin1, Po-Jung Chen1, Tsen-Hsiang Pan1, De-Qi You1, Fang-Yi Chen1, Andrew Lee1, Chung-Chuan Lo1, Ren-Shuo Liu1, Chih-Cheng Hsieh1, Kea-Tiong Tang1, Yu-Der Chih3, Tsung-Yung Chang3, Meng-Fan Chang1,2
ISSCC 2023 Session 33 AI / ML
A 9Mb HZO-Based Embedded FeRAM with 1012-Cycle Endurance and 5/7ns Read/Write using ECC-Assisted Data Refresh and Offset-Canceled Sense Amplifier
Jianguo Yang1, Qing Luo1, Xiaoyong Xue2, Haijun Jiang3, Qiqiao Wu2,
University, Shanghai, China 3 Zhejiang Lab, Hangzhou, China 1 voltage (VT) has a positive coefficient of about +0.085mV/°C. By setting a proper R2:R3 ratio, a tracking voltage (Vtrack) can be generated with an expected r
Zhongze Han1, Yue Cao3, Yongkang Han3, Chunmeng Dou1, Hangbing Lv1, Qi
ISSCC 2023 Session 33 AI / ML
A 28nm 2Mb STT-MRAM Computing-in-Memory Macro with a Refined Bit-Cell and 22.4 – 41.5TOPS/W for AI Inference
Hao Cai1, Zhongjian Bian1, Yaoru Hou1, Yongliang Zhou1, Jia-le Cui1,
Emerging non-volatile memory-based computing-in-memory (CIM) is an excellent fit for resource-constrained edge-AI devices [1-6]. MRAM-CIM macros for MAC operations, at present, rely on a crossbar structure or a periphera
Yanan Guo1, Xiaoyun Tian1, Bo Liu1, Xin Si1, Zhen Wang2, Jun Yang1, We
ISSCC 2023 Session 34 Quantum & Photonics
THz Cryo-CMOS Backscatter Transceiver: A Contactless 4 Kelvin-300 Kelvin Data Interface
Jinchen Wang, Mohamed I. Ibrahim, Isaac B. Harris, Nathan M. Monroe,
Muhammad Ibrahim Wasiq Khan, Xiang Yi, Dirk R. Englund, Ruonan Han Massachusetts Institute of Technology, Cambridge, MA Modern low-temperature large-scale systems, such as high-sensitivity IR/THz imaging arrays and quant
ISSCC 2023 Session 34 Quantum & Photonics
A 28-nm Bulk-CMOS IC for Full Control of a Superconducting Quantum Processor Unit-Cell
Juhwan Yoo1, Zijun Chen1, Frank Arute1, Shirin Montazeri1, Marco Szalay1,
Catherine Erickson1, Evan Jeffrey1, Reza Fatemi1, Marissa Giustina1, Markus Ansmann1, Erik Lucero1, Julian Kelly1, Joseph C. Bardin1,2 Google Quantum AI, Goleta, CA University of Massachusetts, Amherst, MA 1 2 While larg
ISSCC 2023 Session 34 Quantum & Photonics
A Polar-Modulation-Based Cryogenic Qubit State Controller in 28nm Bulk CMOS
Yanshu Guo1,2, Yaoyu Li1, Wenqiang Huang1, Songyao Tan1, Qichun Liu3,
Quantum Information Sciences, Beijing, China 1 2 In today’s mainstream superconducting quantum computing platforms in a dilution refrigerator, the qubits work at a cryogenic temperature (CT) of a few tens of mK, while th
Tiefu Li1,3, Ning Deng1, Zhihua Wang1, Yuanjin Zheng2, Hanjun Jiang1 T
ISSCC 2023 Session 34 Quantum & Photonics
A Cryogenic Controller IC for Superconducting Qubits with DRAG Pulse Generation by Direct Synthesis without Using Memory
Kiseo Kang, Donggyu Minn, Jaeho Lee, Ho-Jin Song, Moonjoo Lee, Jae-Yoon Sim
superconducting qubits foresee reaching the next milestones of the exponentially growing number of qubits. The promises in the scalability present opportunities in integrated control electronics operating at 4K stage in
Pohang University of Science and Technology, Pohang, Korea Recent achi
ISSCC 2023 Session 34 Quantum & Photonics
A Calibration-Free 12.8-16.5GHz Cryogenic CMOS VCO with 202dBc/Hz FoM for Classic-Quantum Interface
Gengnanyang Zhang1, Haichuan Lin2, Cheng Wang1
Chengdu Data Automation System Technologies, Chengdu, China 1 Recently, physical quantum-bits (Qubits) have achieved a remarkable operational fidelity >99.9% and a coherence time ranging from milliseconds to seconds with
University of Electronic Science and Technology of China, Chengdu, Chi
ISSCC 2023 Session 4 Clocking & PLLs
A 135fsrms-Jitter 0.6-to-7.7GHz LO Generator Using a Single LC-VCO-Based Subsampling PLL and a Ring-Oscillator-Based Sub-Integer-N Frequency Multiplier
Yongwoo Jo*, Juyeop Kim*, Yuhwan Shin, Chanwoong Hwang, Hangi Park, Jaehyouk Choi
bands are still the primary spectrum for 5G communications due to their natural advantages, such as higher compatibility/interoperability with existing networks and better properties for radio transmission. To fully util
Korea Advanced Institute of Science and Technology, Daejeon, Korea *Eq
ISSCC 2023 Session 4 Clocking & PLLs
A 76.7fs-Integrated-Jitter and -71.9dBc In-Band FractionalSpur Bang-Bang Digital PLL Based on an Inverse-ConstantSlope DTC and FCW Subtractive Dithering
Simone M. Dartizio1, Francesco Tesolin1, Giacomo Castoro1,
Luca Bertulessi1, Carlo Samori1, Andrea L. Lacaita1, Salvatore Levantino1 Politecnico di Milano, Milano, Italy, 2Infineon Technologies, Villach, Austria 1 Ultra-low-jitter and high-spectral-purity frequency synthesizers
Francesco Buccoleri1, Luca Lanzoni1, Michele Rossoni1, Dmytro Cherniak
ISSCC 2023 Session 4 Clocking & PLLs
A 32kHz-Reference 2.4GHz Fractional-N Nonuniform Oversampling PLL with Gain-Boosted PD and Loop-Gain Calibration constructed DAC voltage (VDAC) is shaped with a high slope (SDAC) in the gain-boosted PD, a high SDAC is achieved by generating a slope on VDAC in the gain-boosted PD, and the DTC delay is used to compensate for the timing error from CLKFB to the voltage crossing.
Junjun Qiu, Wenqian Wang, Zheng Sun, Bangan Liu, Yuncheng Zhang,
Dingxin Xu, Hongye Huang, Ashbir Aviat Fadila, Zezheng Liu, Waleed Madany, Yuang Xiong, Atsushi Shirane, Kenichi Okada Figure 4.4.3 illustrates the proposed gain-boosted PD. In the conventional OSPLL, the slew rate of th
ISSCC 2023 Session 4 Clocking & PLLs
A 9.25GHz Digital PLL with Fractional-Spur Cancellation Based on a Multi-DTC Topology
Giacomo Castoro*1, Simone M. Dartizio*1, Francesco Tesolin1,
Carlo Samori1, Andrea L. Lacaita1, Salvatore Levantino1 Politecnico di Milano, Milan, Italy, 2Infineon Technologies, Villach, Austria *Equally Credited Authors (ECAs) 1 The quest of increasingly higher mobile uplink/down
Francesco Buccoleri1, Michele Rossoni1, Dmytro Cherniak2, Luca Bertule
ISSCC 2023 Session 4 Clocking & PLLs
A 47fsrms-Jitter and 26.6mW 103.5GHz PLL with Power-Gating Injection-Locked Frequency-Multiplier-Based Phase Detector and Extended Loop Bandwidth
Jooeun Bang, Jaeho Kim, Seohee Jung, Suneui Park, Jaehyouk Choi
The W and D bands located at the lower boundary of the sub-THz spectrum are considered viable candidates for CMOS-based wireless-communication systems to utilize sub-THz frequencies. However, there are still many challen
Korea Advanced Institute of Science and Technology, Daejeon, Korea
ISSCC 2023 Session 4 Clocking & PLLs
A 0.4V-VDD 2.25-to-2.75GHz ULV-SS-PLL Achieving 236.6fsrms
Jitter, -253.8dB Jitter-Power FoM, and -76.1dBc Reference, Spur
Zhao Zhang1, Xinyu Shen1, Zhaoyu Zhang1, Guike Li1, Nan Qi1, Jian Liu1, Yong Chen2, Nanjian Wu1, Liyuan Liu1 Institute of Semiconductors, Chinese Academy of Sciences, Beijing, China University of Macau, Macau, China 1 2
ISSCC 2023 Session 5 Image Sensors
A 3-Wafer-Stacked Hybrid 15MPixel CIS + 1MPixel EVS with
4.6GEvent/s Readout, In-Pixel TDC and On-Chip ISP and ESP, Function
Menghan Guo1, Shoushun Chen1, Zhe Gao2, Wenlei Yang1, Peter Bartkovjak2, Qing Qin2, Xiaoqin Hu1, Dahei Zhou1, Masayuki Uchiyama2, Yoshiharu Kudo3, Shimpei Fukuoka3, Chengcheng Xu2, Hiroaki Ebihara2, Andy Wang2, Peiwen Ji
ISSCC 2023 Session 5 Image Sensors
µm 35.6Mpixel RGB Hybrid Event-Based Vision Sensor with 4.88µm-Pitch Event Pixels and up to 10K Event Frame Rate by Adaptive Control on Event Sparsity
Kazutoshi Kodama1, Yusuke Sato1, Yuhi Yorikado1, Raphael Berner2,
Kyoji Mizoguchi1, Takahiro Miyazaki1, Masahiro Tsukamoto1, Yoshihisa Matoba1, Hirotaka Shinozaki1, Atsumi Niwa1, Tetsuji Yamaguchi1, Christian Brandli2, Hayato Wakabayashi1, Yusuke Oike1 Sony Semiconductor Solutions, Ats
ISSCC 2023 Session 5 Image Sensors
A 2.97µm-Pitch Event-Based Vision Sensor with Shared Pixel Front-End Circuitry and Low-Noise Intensity Readout Mode
Atsumi Niwa1, Futa Mochizuki1, Raphael Berner2, Takuya Maruyama1,
Toshio Terano1, Kenichi Takamiya1, Yasutaka Kimura1, Kyoji Mizoguchi1, Takahiro Miyazaki1, Shun Kaizu1, Hirotsugu Takahashi1, Atsushi Suzuki1, Christian Brandli2, Hayato Wakabayashi1, Yusuke Oike1 Sony Semiconductor Solu
ISSCC 2023 Session 5 Image Sensors
A 0.64µm 4-Photodiode 1.28µm 50Mpixel CMOS Image Sensor with 0.98e- Temporal Noise and 20Ke- Full-Well Capacity Employing Quarter-Ring Source-Follower
Hyuncheol Kim, Yun Hyeok Kim, Sanghyuck Moon, Hwanwoong Kim,
Byeongjun Yoo, Jueun Park, Seyoung Kim, June-Mo Koo, Sewon Seo, Hye Ji Shin, Younghwan Choi, Jinwoo Kim, Kyungil Kim, Jae-Hoon Seo, Seunghyun Lim, Taesub Jung, Howoo Park, Sangil Jung, Juhyun Ko, Kyungho Lee, JungChak Ah
ISSCC 2023 Session 5 Image Sensors
A 16.4kPixel 3.08-to-3.86THz Digital Real-Time CMOS Image Sensor with 73dB Dynamic Range
Min Liu1, Ziteng Cai1, Shaohua Zhou2, Man-Kay Law3, Jian Liu1, Jianguo Ma4,
Terahertz (THz) imaging has promising applications in chemical and biomedical systems, industrial defect inspection, security screening, and radio astronomy owing to its favorable resolution and nondestructive features [
Nanjian Wu1, Liyuan Liu1 Chinese Academy of Sciences, Beijing, China T
ISSCC 2023 Session 5 Image Sensors
A 400×200 600fps 117.7dB-DR SPAD X-Ray Detector with Seamless Global Shutter and Time-Encoded Extrapolation Counter
Byungchoul Park1, Byungwook Ahn1, Hyun-Seung Choi2, Jinwoong Jeong3,
overflow, and hence an active reset is implemented with a reset transistor MAQ and the pixel supply voltage VPIX (=3.3V), a higher voltage than VEX. The buffered SPAD output φSPAD is fed to either counter A or B via inpu
Kangmin Hwang3, Taewoo Kim3, Myung-Jae Lee2, Youngcheol Chae1 Yonsei U
ISSCC 2023 Session 5 Image Sensors
55pW/pixel Peak Power Imager with Near-Sensor Novelty/Edge Detection and DC-DC Converter-Less MPPT for Purely Harvested Sensor Nodes
Karim Ali Ahmed*, Hayate Okuhara*, Massimo Alioto
*Equally Credited Authors (ECAs) Cost and form factor reductions in CMOS imagers are enabling the deployment of increasingly distributed vision sensor systems. Due to battery cost and size, aggressive power reductions ar
National University of Singapore, Singapore, Singapore
ISSCC 2023 Session 5 Image Sensors
Dual-Port CMOS Image Sensor with Regression-Based HDR Flux-to-Digital Conversion and 80ns Rapid-Update Pixel-Wise Exposure Coding
Rahul Gulve, Roberto Rangel, Ayandev Barman, Don Nguyen, Mian Wei,
Motasem A. Sakr, Xiaonong Sun, David B. Lindell, Kiriakos N. Kutulakos, Roman Genov University of Toronto, Toronto, Canada Today’s best consumer cameras typically use computational imaging techniques to digitally enhance
ISSCC 2023 Session 6 Wireline I/O
A 112Gb/s Serial Link Transceiver With 3-tap FFE and 18-tap DFE Receiver for up to 43dB Insertion Loss Channel in 7nm FinFET Technology
Bo Zhang1, Anand Vasani1, Ashutosh Sinha2, Alireza Nilchi1, Haitao Tong1,
Lakshmi Rao1, Karapet Khanoyan1, Hamid Hatamkhani1, Xiaochen Yang1, Xin Meng1, Alexander Wong2, Jun Kim2, Ping Jing2, Yehui Sun2, Ali Nazemi1, Dean Liu2, Anthony Brewster1, Jun Cao1, Afshin Momtaz1 Broadcom, Irvine, CA B
ISSCC 2023 Session 6 Wireline I/O
A 4.63pJ/b 112Gb/s DSP-Based PAM-4 Transceiver for a Large-Scale Switch in 5nm FinFET detection can either use a low-latency short FFE to minimize peaking in the jitter transfer curve or use the main FFE/DFE output for very high loss channels (> 40dB).
Henry Park*1, Mohammed Abdullatif*1, Ehung Chen1, Ahmed Elmallah1,
Qaiser Nehal1, Miguel Gandara1, Tsz-Bin Liu2, Amr Khashaba1, Joonyeong Lee1, Chih-Yi Kuan2, Dhinessh Ramachandran1, Ruey-Bo Sun2, Atharav Atharav1, Yusang Chun1, Mantian Zhang1, Deng-Fu Weng2, Chung-Hsien Tsai2, Chen-Hao
ISSCC 2023 Session 6 Wireline I/O
A 0.43pJ/b 200Gb/s 5-Tap Delay-Line-Based Receiver FFE with Low-Frequency Equalization in 28nm CMOS
Bingyi Ye, Guangdong Wu, Weixin Gai, Kai Sheng, Yandong He
The ever-increasing demand for greater I/O bandwidth has pushed the transceiver data rate to 200Gb/s [1]. At this rate, the implementation of decision-feedback equalizers faces severe timing constraints. Discrete-time fe
Peking University, Beijing, China
ISSCC 2023 Session 6 Wireline I/O
A 4nm 32Gb/s 8Tb/s/mm Die-to-Die Chiplet Using NRZ Single-Ended Transceiver With Equalization Schemes And Training Techniques
Kihwan Seong, Donguk Park, Gyeomje Bae, Hyunwoo Lee, Youngseob Suh,
Wooseuk Oh, Hyemun Lee, Juyoung Kim, Takgun Lee, Geonhoo Mo, Sukhyun Jung, Dongcheol Choi, Byoung-Joo Yoo, Sanghune Park, Hyo-Gyuem Rhew, Jongshin Shin Samsung Electronics, Hwasung, Korea Recently, the demand for multi-c
ISSCC 2023 Session 6 Wireline I/O
A 37.8dB Channel Loss 0.6µs Lock Time CDR with Flash Frequency Acquisition in 5nm FinFET
Chien-Kai Kao, Shih-Che Hung, Tse-Hsien Yeh, Chen-Yu Hsiao
High-speed SerDes is accompanied by high channel loss. Channel loss is usually compensated by transmitter feed-forward equalization (FFE), receiver continuous time linear equalization (CTLE), and receiver decision-feedba
MediaTek, Hsinchu, Taiwan
ISSCC 2023 Session 6 Wireline I/O
A 0.83pJ/b 52Gb/s PAM-4 Baud-Rate CDR with Pattern-Based Phase Detector for Short-Reach Applications one point. VREFPM is set slightly above h0, and VREFPN is set slightly under $h0 for the optimal point. In this work, a single-stage CTLE is implemented for an energy-efficient equalizer, and the second lock option is chosen.
Seungwoo Park, Yoonjae Choi, Jincheol Sim, Jonghyuck Choi, Hyunsu Park,
Youngwook Kwon, Chulwoo Kim Figure 6.6.4 shows the circuit implementation and the operation of the data recovery path. The detailed operation is illustrated as two phases (CK0,90) in simulated transient waveforms. A conv
ISSCC 2023 Session 6 Wireline I/O
A 128Gb/s PAM-4 Transmitter with Programmable-Width Pulse Generator and Pattern-Dependent Pre-Emphasis in 28nm CMOS
Kai Sheng, Weixin Gai, Zeze Feng, Haowei Niu, Bingyi Ye, Hang Zhou
The ever-growing demands for high-bandwidth communications continuously push wireline links to operate at higher speeds. Recently reported transmitters (TXs) have achieved a data rate of more than 100Gb/s [1-6]. PAM-4 mo
Peking University, Beijing, China
ISSCC 2023 Session 6 Wireline I/O
A 100Gb/s 1.6Vppd PAM-8 Transmitter with High-Swing 3+1 Hybrid FFE Taps in 40nm the selected FFE setting, with proper shift operations involved. This approach minimizes the area and power overhead for the FFE multiplexing, while still covering a sufficient range of configurations for representative channels.
Jeonghyu Yang*, Eunji Song*, Seungwook Hong, Dongjun Lee, Sangwan Lee,
Hyunwoo Im, Taeho Shin, Jaeduk Han The FIR controller output and the N-bit shifted MSB signals are further upconverted by the following ten 8:4 serializers, producing a 40-bit data stream (TA4, TB4, and TC4 for the norma
ISSCC 2023 Session 7 AI / ML
A 22nm 832Kb Hybrid-Domain Floating-Point SRAM In-Memory-Compute Macro with 16.2-70.2TFLOPS/W for High-Accuracy AI-Edge Devices
Ping-Chun Wu*1, Jian-Wei Su*1,2, Li-Yang Hong1, Jin-Sheng Ren1,
Chih-Han Chien1, Ho-Yu Chen1, Chao-En Ke1, Hsu-Ming Hsiao2, Sih-Han Li2, Shyh-Shyuan Sheu2, Wei-Chung Lo2, Shih-Chieh Chang2, Chung-Chuan Lo1, Ren-Shuo Liu1, Chih-Cheng Hsieh1, Kea-Tiong Tang1, Meng-fan Chang1 National T
ISSCC 2023 Session 7 AI / ML
A 28nm 64-kb 31.6-TFLOPS/W Digital-Domain Floating-PointComputing-Unit and Double-Bit 6T-SRAM Computing-inMemory Macro for Floating-Point CNNs
An Guo, Xin Si, Xi Chen, Fangyuan Dong, Xingyu Pu, Dongqi Li,
Yongliang Zhou, Lizheng Ren, Yeyang Xue, Xueshan Dong, Hui Gao, Yiran Zhang, Jingmin Zhang, Yuyao Kong, Tianzhu Xiong, Bo Wang, Hao Cai, Weiwei Shan, Jun Yang Southeast University, Nanjing, China SRAM-based computing-in-
ISSCC 2023 Session 7 AI / ML
A 28nm 38-to-102-TOPS/W 8b Multiply-Less Approximate Digital SRAM Compute-In-Memory Macro for Neural-Network Inference
Yifan He1, Haikang Diao2, Chen Tang1, Wenbin Jia1, Xiyuan Tang2, Yuan Wang2,
2 This paper presents a 2-to-8-b scalable digital SRAM-based CIM macro that is codesigned with a multiply-less neural-network (NN) design methodology and incorporates dynamic-logic-based approximate circuits for vector-v
Jinshan Yue3, Xueqing Li1, Huazhong Yang1, Hongyang Jia1, Yongpan Liu1
ISSCC 2023 Session 7 AI / ML
A 4nm 6163-TOPS/W/b 4790-TOPS/mm2/b SRAM Based Digital-Computing-in-Memory Macro Supporting Bit-Width Flexibility and Simultaneous MAC and Weight Update disabled, to save power, in 8b mode. The INWIDTH[1:0] bus controls the XIN width: 00 for 8b, 01 for 12b, and 10 for 16b modes. To support a signed format with width flexibility, the first 4 cycles are signed 4b operations and the rest of the cycles are unsigned 4b operations, regardless of INWIDTH.
Haruki Mori1, Wei-Chang Zhao1, Cheng-En Lee1, Chia-Fu Lee1, Yu-Hao Hsu1,
Chao-Kai Chuang1, Takeshi Hashizume2, Hao-Chun Tung1, Yao-Yi Liu1, Shin-Rung Wu1, Kerem Akarvardar3, Tan-Li Chou1, Hidehiro Fujiwara1, Yih Wang1, Yu-Der Chih1, Yen-Huei Chen1, Hung-Jen Liao1, Tsung-Yung Jonathan Chang1 F
ISSCC 2023 Session 7 AI / ML
A 28nm Horizontal-Weight-Shift and Vertical-Feature-ShiftBased Separate-WL 6T-SRAM Computation-in-Memory Unit-Macro for Edge Depthwise Neural-Networks
Bo Wang, Chen Xue, Zhongyuan Feng, Zhaoyang Zhang, Han Liu, Lizheng Ren,
Xiang Li, Anran Yin, Tianzhu Xiong, Yeyang Xue, Shengnan He, Yuyao Kong, Yongliang Zhou, An Guo, Xin Si, Jun Yang Southeast University, Nanjing, China SRAM-based computation-in-memory (CIM) has shown great potential in i
ISSCC 2023 Session 7 AI / ML
A 70.85–86.27TOPS/W PVT-Insensitive 8b Word-Wise ACIM with Post-Processing Relaxation
end of the compute phase, the converted voltage (V8bink = Dink[7:0] × VREF /(16 × 17)) is, buffered into the SRAM array
the 16× reduction of the global VREF routing (from 8b 256 nodes to 16 nodes), the area is 16× smaller. Without the multi-conversions of MSB/LSB parts and digital bit shifting, the clock complexity, gain, offset, linearit
ISSCC 2023 Session 7 AI / ML
CV-CIM: A 28nm XOR-Derived Similarity-Aware Computation-in-Memory for Cost-Volume Construction
Zhiheng Yue, Yang Wang, Huizheng Wang, Yabing Wang, Ruiqi Guo,
pixels in paired images, is a fundamental kernel of stereo vision processing and has been directly used in robotic, autopilot, and AR/VR applications. However, the large parameter size and consecutive data accesses of re
Limei Tang, Leibo Liu, Shaojun Wei, Yang Hu, Shouyi Yin Tsinghua Unive
ISSCC 2023 Session 7 AI / ML
A 22nm Delta-Sigma Computing-In-Memory (∆ΣCIM) SRAM Macro with Near-Zero-Mean Outputs and LSB-First ADCs Achieving 21.38TOPS/W for 8b-MAC Edge AI Processing
Peiyu Chen*1, Meng Wu*1, Wentao Zhao1, Jiajia Cui1, Zhixuan Wang1,2,
Peking University, Hangzhou, China, 3 Nano Core Chip Electronic Technology, Hangzhou, China *Equally Credited Authors (ECAs) 1 2 In AI-edge devices, the changes of input features are normally progressive or occasional, e
Yadong Zhang3, Qijun Wang3, Jiayoon Ru1, Linxiao Shen1, Tianyu Jia1, Y
ISSCC 2023 Session 7 AI / ML
CTLE-Ising: A 1440-Spin Continuous-Time Latch-Based Ising Machine with One-Shot Fully-Parallel Spin Updates Featuring Equalization of Spin States
Jooyoung Bae*, Wonsik Oh*, Jahyun Koo, Bongjin Kim
*Equally Credited Authors (ECAs) The Ising machine is a hardware accelerator that finds solutions to combinatorial optimization problems (COPs) using the natural convergence behavior of the Ising model, which comprises a
University of California, Santa Barbara, CA
ISSCC 2023 Session 8 mm-Wave
An 11.5-to-14.3GHz 192.8dBc/Hz FoM at 1MHz Offset Dual-Core Enhanced Class-F VCO with Common-Mode-Noise Self-Cancellation and Isolation Technique
Qixiu Wu, Wei Deng, Haikun Jia, Hongzhuo Liu, Shiwei Zhang, Zhihua Wang, Baoyong Chi
stricter requirements on the power consumption, silicon area, and phase noise specifications for local oscillators (LOs) in mobile and portable devices, especially in battery-powered mobile phones, notebook computers, an
Tsinghua University, Beijing, China The current 5G and future 6G high-
ISSCC 2023 Session 8 mm-Wave
A 22.4-to-26.8GHz Dual-Path-Synchronized Quad-Core Oscillator Achieving −138dBc/Hz PN and 193.3dBc/Hz FoM at 10MHz Offset from 25.8GHz If the frequency mismatch exists in the adjacent cores (f1 = f3 > f2 = f4), a strong coupling (k2) between LG13 and LG24 also helps reduce the output amplitude variation. Consequently, the PN penalty of our dual-path-synchronized oscillator is ~0dB at a 5% frequency mismatch, which is even lower than that of the conventional design (0.2dB).
Xiangxun Zhan1, Jun Yin1, Pui-In Mak1, Rui P. Martins1,2, To design the transformer tank, we can assume no frequency mis
four cores and connect VGP1-4 (VGN1-4, VDP1-4, and VDN1-4) together. Then the quad-core oscillator can be equivalent to a dual-core oscillator in Fig. 8.2.3 (top-left). The triplecoil transformer in the dual-core oscilla
ISSCC 2023 Session 8 mm-Wave
A 28GHz Scalable Inter-Core-Shaping Multi-Core Oscillator with DM/CM-Configured Coupling Achieving 193.3dBc/Hz FoM and 205.5dBc/Hz FoMA at 1MHz Offset
Yiyang Shu, Zhixian Deng, Xun Luo
The high-order modulation schemes of mm-wave wireless communication networks (e.g., 5GNR) have stringent requirements for the LO phase noise. Besides, to minimize the power consumption of oscillators, a high figure-of-me
University of Electronic Science and Technology of China, Chengdu, Chi
ISSCC 2023 Session 8 mm-Wave
An 83.3-to-104.7GHz Harmonic-Extraction VCO Incorporating
Multi-Resonance, Multi-Core, and Multi-Mode (3M), Techniques Achieving -124dBc/Hz Absolute PN and
190.7dBc/Hz FoMT Hao Guo1, Yong Chen1, Yunbo Huang1, Pui-In Mak1, Rui P. Martins1,2 University of Macau, Macau, China Instituto Superior Tecnico/University of Lisboa, Lisbon, Portugal 1 2 The W-band offers a rich spectru
ISSCC 2023 Session 9 Industry Highlights
D1: A 7nm ML Training Processor with Wave Clock Distribution
Tim C. Fischer1, Anantha Kumar Nivarti1, Raghuvir Ramachandran1,
Ram Bharti1, Derek Carson1, Anton Lawrendra1, Vineet Mudgal1, Vivek Santhosh1, Sunil Shukla2, Te-Chen Tsai1 Tesla, Palo Alto, CA Tesla, Austin, TX 1 2 D1 is the ML training processor in the DOJO exa-scale computer system
ISSCC 2023 Session 9 AI / ML
A 1mW Always-on Computer Vision Deep Learning Neural Decision Processor
David Garrett, Youn Sung Park, Seongjong Kim, Jay Sharma, Wenbin Huang,
Majid Shaghaghi, Vinay Parthasarathy, Stephen Gibellini, Stephen Bailey, Mallik Moturi, Pieter Vorenkamp, Kurt Busch, Jeremy Holleman, Behrooz Javid, Alireza Yousefi, Mohsen Judy, Atul Gupta Syntiant, Irvine, CA Syntiant
ISSCC 2023 Session 9 Industry Highlights
NVLink-C2C: A Coherent Off Package Chip-to-Chip Interconnect with 40Gbps/pin Single-ended Signaling
Ying Wei1, Yi Chieh Huang2, Haiming Tang1, Nithya Sankaran1, Ish Chadha1,
systems, with 900GB/s link between Grace and Hopper, or between two Grace chips. The connection provides a unified, cache-coherent memory address space that combines system and HBM GPU memories for simplified programmabi
Dai Dai1, Olakanmi Oluwole1, Vishnu Balan1, Edward Lee1 Nvidia, Santa
ISSCC 2023 Session 9 Industry Highlights
An In-depth Look at the Intel IPU E2000
Naru Sundar*1, Brad Burres*2, Yadong Li*3, Dave Minturn4, Brian Johnson4, Nupur Jain5
Processing Unit (Intel IPU) E2000 is Intel’s first ASIC IPU device, a 200G product co-designed with Google and in production as of 2022. It features a rich packet processing pipeline, RDMA and storage capability includin
Intel, Santa Clara, CA Intel, Hudson, MA 3 Intel, Portland, OR 4 Intel