ISSCC 2024

2024

222 篇论文 · AI / ML (33) · Power Management (30) · RF & Wireless (28) · Digital Processors (15)

ISSCC 2024 Session 7 Wireline I/O
A 2.16pJ/b 112Gb/s PAM-4 Transceiver with Time-Interleaved 2b/3b ADCs and Unbalanced Baud-Rate CDR for XSR Applications in 28nm CMOS
Yen-Po Lin*, Pen-Jui Peng*, Chun-Chang Lu, Po-Ting Shen, Yun-Cheng Jao, Ping-Hsuan Hsieh
serializer-deserializer (SerDes) transceivers for >100Gb/s data rates have been developed in recent years [1-4]. Differing from the medium-reach (MR) or long-reach (LR) applications, the XSR TRX targets <50mm traces for
National Tsing Hua University, Hsinchu, Taiwan *Equally Credited Autho
ISSCC 2024 Session 7 Wireline I/O
A 69.3fs Ring-Based Sampling-PLL Achieving 6.8GHz-14GHz and -54.4dBc Spurs Under 50mV Supply Noise
Mahmoud A. Khalil, Mohamed Badr Younis, Ruhao Xia,
Ahmed E. Abdelrahman, Tianyu Wang, Kyu-Sang Park, Pavan Kumar Hanumolu University of Illinois, Urbana, IL A low-jitter multi-phase clock generator is pivotal in high-speed serial link transceivers. With data rates surpas
ISSCC 2024 Session 7 Wireline I/O
An 8b 6-12GHz 0.18mW/GHz DC Modulated Ramp-Based Phase Interpolator in 65nm CMOS Process receiving injections. Further, the quadrature outputs from the 4-phase signals from the RO are edge-combined using an XOR gate to produce differential outputs with twice the RO frequency as shown in Fig. 7.9.2.
Soumen Mohapatra, Emad Afshar, Zhiyuan Zhou, Deukhyoun Heo, Figure 7.9.3 shows a detailed circuit diagram of the ramp ge
capacitor current based on the differential input clocks to generate differential ramp signals. The internal loop within the replica bias sets the DC level of the ramp signal. To ensure the ramp’s linearity across proces
ISSCC 2024 Session 8 Power Management
A 94.5%-Peak-Efficiency 3.99W/mm2-Power-Density Single-Inductor Bipolar-Output Converter with a Concise PWM Control for AMOLED Displays
Ji Jin*1, Weiwei Xu*2, Lin Cheng1,2
Hefei CLT Microelectronics, Hefei, China *Equally Credited Authors (ECAs) 1 2 DC-DC converters with bipolar outputs are widely used to drive AMOLED displays in battery-powered electronic devices. To prolong the battery l
University of Science and Technology of China, Hefei, China
ISSCC 2024 Session 8 Power Management
A 5V-to-150V Input-Parallel Output-Series Hybrid DC-DC Boost Converter Achieving 76.4mW/mg Power Density and 80% Peak Efficiency
Shousheng Han1,2, Zanfeng Fang1, Zhiguo Tong1, Xiaoming Wu2, Hanjun Jiang2,
essential for biomedical, optics, sensing and diagnostics applications. For realizing an ultrahigh VCR, the conventional boost converter would result in a large duty ratio D, a large inductor current IL and thus a signifi
Tianling Ren2, Yan Lu1 University of Macau, Macau, China Tsinghua Univ
ISSCC 2024 Session 8 Power Management
A 48V-to-5V Buck Converter with Triple EMI Suppression Circuit Meeting CISPR 25 Automotive Standards existing at VSW can be largely suppressed, which reduces high-frequency EMI amplitude (bottom right of Fig. 8.11.2).
Yi-Hsiang Kao , Chieh-Sheng Hung , Hui-Hsuan Chang , Wei-Cheng Huang ,
Rong-Bin Guo1, Hsing-Yen Tsai1, Ke-Horng Chen1, Kuo-Lin Zeng1,2, Ying-Hsi Lin3, Shian-Ru Lin3, Tsung-Yen Tsai3 1 1 1 1 National Yang Ming Chiao Tung University, Hsinchu, Taiwan Chip-GaN Power Semiconductor, Hsinchu, Taiw
ISSCC 2024 Session 8 Power Management
A 96.9%-Peak-Efficiency Bilaterally-Symmetrical Hybrid Buck-Boost Converter Featuring Seamless Single-Mode
Operation, Always-Reduced Inductor Current, and the Use, of All CMOS Switches
use batteries. It works by regulating the output voltage (VO = 3.4V) with a specific voltage conversion ratio (M = VO/VIN), given a supplied voltage (VIN = 2.7 ~ 4.2V) that fluctuates based on the battery’s state-of-charge
Dae-Hyeon Kim, Hyun-Sik Kim Korea Advanced Institute of Science and Te
ISSCC 2024 Session 8 Power Management
A Li-ion-Battery-Input 1-to-6V-Output Bootstrap-Free Hybrid Buck-or-Boost Converter Without RHP Zero Achieving 97.3% Peak Efficiency 6μs Recovery Time and 1.13μs/V DVS Rate
Junyi Ruan1, Junmin Jiang2, Chenzhou Ding1, Kai Yuan1, Ka Nang Leung3, Xun Liu1
today’s mobile devices, buck-boost converters are widely used to convert the Li-ion battery voltage (VIN), typically ranging from 2.7 to 4.2V, to the specific output voltage (VO) levels required by various modules. While
Chinese University of Hong Kong, Shenzhen, China Southern University o
ISSCC 2024 Session 8 Power Management
A Fast-Transient 3-Fine-Level Buck-Boost Hybrid DC-DC Converter with Half-Voltage-Stress on All Switches and 98.2% Peak Efficiency
Shuangxing Zhao1,2, Chenchang Zhan2, Yan Lu1
Southern University of Science and Technology, Shenzhen, China 1 Figure 8.4.3 exhibits the overall structure of the proposed buck-boost converter including the power stage and control stage. All circuits are implemented
University of Macau, Macau, China
ISSCC 2024 Session 8 Power Management
An Integrated Dual-side Series/Parallel Piezoelectric Resonator-based 20-to-2.2V DC-DC Converter Achieving a 310% Loss Reduction
Wen-Chin Brian Liu1, Gaël Pillonnet2, Patrick P. Mercier1
CEA-Léti, Grenoble, France 1 2 Piezoelectric resonators (PRs) have recently emerged as an attractive substitute for inductors to process energy in DC-DC converters, due to their low-volume planar formfactors, superior vo
University of California, San Diego, CA
ISSCC 2024 Session 8 Power Management
A 92.7% Peak Efficiency 12V-to-60V Input to 1.2V Output Hybrid DC-DC Converter Based on a Series-Parallel-Connected Switched Capacitor
Hyeon-Ji Choi1, Chan-Ho Lee1, Young-Jun Jeon1, Hyeonho Park1,
automotive applications for a higher efficiency power system. Accordingly, an ultra-low voltage-conversion-ratio (VCR) buck converter is in great demand. Previous ultra-low VCR buck converters use flying capacitors (CFs) a
Jeong-Hun Kim1, Young-Jin Woo2, Ju-Pyo Hong2, Haifeng Jin2, Sung-Wan H
ISSCC 2024 Session 8 Power Management
A 97.18% Peak-Efficiency Asymmetrically Implemented Dual-phase (AID) Converter with a full Voltage-Conversion Ratio (VCR) between 0-and-1
Hyo-Jin Park1, Joo-Mi Cho1, Chan-Ho Lee1, Young-Ju Oh1, Hyunwoo Jeong1,
smaller and need to achieve a higher performance, a DC-DC converter using a small-size inductor (L) has become necessary. Accordingly, as shown in Fig. 8.8.1, previous researches have suggested various methods to achieve
Jun-Hyeok Yang2, Jaeseung Lee2, Sung-Wan Hong1 Sogang University, Seou
ISSCC 2024 Session 8 Power Management
A 96.5% Peak Efficiency Duty-Independent DC-DC Step-Up Converter with Low Input-Level Voltage Stress and Mode-Adaptive Inductor Current Reduction
Minsu Kim1, Woojoong Jung1, Hyunjun Park1, Junho Song1,2, Youngkook Ahn2,
to efficiently convert a low input voltage (VIN) to a higher output voltage (VOUT) in USB- or battery-powered mobile systems, including battery chargers (10 to 13V), OLED drivers (5 to 13V), etc. The conventional boost co
Taekyu Nam2, Yoonsoo Shin2, Young-Jin Woo2, Hyung-Min Lee1 Korea Unive
ISSCC 2024 Session 9 Data Converters
A 2mW 70.7dB SNDR 200MS/s Pipelined-SAR ADC with Continuous-Time SAR-Assisted Detect-and-Skip and Open-then-Close Correlated Level Shifting
Siyuan Ye1, Linxiao Shen1, Jihang Gao1, Jie Li1, Zhuoyi Chen1, Xinhang Xu1,
Information Technology of Peking University, Hangzhou, China 1 2 The pipelined-SAR ADC has become popular in wide-bandwidth and high-resolution applications due to its power-efficient architecture [1]. In the pursuit of h
Jiajia Cui1, Hao Zhang2, Xing Zhang1, Le Ye1,3, Ru Huang1 Peking Unive
ISSCC 2024 Session 9 Data Converters
A 2.08mW 64.4dB SNDR 400MS/s 12b Pipelined-SAR ADC using Mismatch and PVT Variation Tolerant Dynamically Biased Ring Amplifier in 8nm
Yong Lim*, Jaehoon Lee*, Jongmi Lee, Kwangmin Lim, Seunghyun Oh,
energy-efficient alternatives to OTAs for switchedcapacitor residue amplifiers. A ring amplifier is essentially a cascaded multi-stage inverter-based amplifier that is stabilized by a dominant pole at the last stage output w
Jongwoo Lee, Sung-Ung Kwak Samsung Electronics, Hwaseong, Korea *Equal
ISSCC 2024 Session 9 Data Converters
A 71dB SNDR 200MHz BW Interleaved Pipe-SAR ADC with a Shared Residue Integrating Amplifier Achieving 173dB FoMs
Xiyu He, Mingyang Gu, Hanjun Jiang, Yi Zhong, Nan Sun, Lu Jie
Wideband (BW >100MHz) and high-dynamic-range (DR >70dB) ADCs are in high demand for next-generation wireless standards. Conventional ADC solutions face challenges in both performance and efficiency: CTDSMs demonstrate fav
Tsinghua University, Beijing, China
ISSCC 2024 Session 9 Data Converters
A 182.3dB FoMs 50MS/s Pipelined-SAR ADC using Cascode Capacitively Degenerated Dynamic Amplifier and MSB Pre-Conversion Technique
Zhuoyi Chen1, Linxiao Shen1, Siyuan Ye1, Jihang Gao1, Jie Li1, Jiajia Cui1,
Information Technology of Peking University, Hangzhou, China 1 2 The residue amplifier (RA) in a pipelined-SAR ADC eases the noise requirement of the back-end stage, making the architecture energy-efficient. However, to ac
Xinhang Xu1, Yaohui Luan1, Hao Zhang2, Le Ye1,3, Ru Huang1 Peking Univ
ISSCC 2024 Session 9 Data Converters
A 118.5dBA DR 3.3mW Audio ADC with a Class-B Resistor
DAC, Non-Overlap DEM and Continuous-Time Quantizer
increased the need for lowpower, high dynamic range (DR) audio ADCs. In these applications, the DR specification determines the maximum distance at which a low-cost microphone can obtain a good quality recording. THD+N (S
Anand Subramanian, Tanmay Halder, Laxmi Vivek Tripurari, Anand Kannan
ISSCC 2024 Session 9 Data Converters
A 6th-Order Quadrature CTDSM using Double-OTA and Quadrature NSSAR with 171.3dB FoMs in 14nm We introduce an extra CC path (shaded blocks in Fig. 9.6.3) to the integrator within NSSAR to achieve even higher SNR. This transforms the NTF of the NSSAR to the desired band, resulting in further suppressed quantization noise in the target bandwidth. Figure 9.6.3 shows the effectiveness of our QNSSAR with the simulated quantization noise using three different quantizers in a quadrature CT-DSM with ideal models. The resulting SQNR utilizing QNSSAR is 93.52dB while the conventional SAR, and NSSAR give 76.35dB, and 88.36dB, respectively.
Jongmi Lee, Seong-Eun Cho, Jaehoon Lee, Yong Lim, Seunghyun Oh,
low-intermediatefrequency (low-IF) architecture is widely chosen for energy efficient wireless communication systems, such as Bluetooth Low Energy (BLE) and IoT. The low-IF architecture typically requires filters for anti-
Jongwoo Lee, Sung-Ung Kwak Samsung Electronics, Hwasung, Korea In orde
ISSCC 2024 Session 9 Data Converters
A 94.3dB SNDR 184dB FoMs 4th-Order Noise-Shaping SAR ADC with Dynamic-Amplifier-Assisted Cascaded Integrator
Kai-Cheng Cheng1, Soon-Jyh Chang1, Chung-Chieh Chen2, Shuo-Hong Hung2
Upbeat Technology, Taipei, Taiwan 1 2 The noise-shaping (NS) SAR ADC, which features the advantages of sigma-delta ADCs and SAR ADCs, is high accuracy and low power, so it stands out as a great choice for audio applicati
National Cheng Kung University, Tainan, Taiwan
ISSCC 2024 Session 9 Data Converters
A 9.3nV/rtHz 20b 40MS/s 94.2dB DR Signal-Chain Friendly Precision SAR Converter
Rares Bodnar1,2, Henry Kennedy1, Christopher P Hurrell1, Asif Ahmad1,
Mark Vickery1, Luke Smithers1, William Buckley3, Monsoon Dutt1, Pasquale Delizia4, Derek Hummerston1, Pawel Czapor3 return high, marking the acquisition of the complementary set of 8 sampling DACs. The remaining timing m
ISSCC 2024 Session 9 Data Converters
A 2.72fJ/conv 13b 2MS/s SAR ADC Using Dynamic Capacitive Comparator with Wide Input Common Mode
Sewon Lee, Hyein Kang, Minjae Lee
As SAR resolution increases, comparator power increases exponentially [1-2]. This problem should be mitigated, especially in battery-powered applications. Recent low power and noise comparators utilized dynamic pre-ampli
Gwangju Institute of Science and Technology, Gwangju, Korea