ISSCC 2025
Session 5
RF & Wireless
A 22nm FDSOI CMOS-Based Compact 3-Stack Doherty Power Amplifier with a Stacked OPA-Based Bias Scheme Achieving >16.5dBm Pavg for 5G FR2 Applications
interest in the millimeter-wave (mm-wave) band. In this frequency range, phased-array systems are crucial for sustaining communication performance despite high propagation loss. In highly integrated phased-array systems,
ISSCC 2025
Session 5
RF & Wireless
An Ultra-Compact Wideband Load-Insensitive Complex-Cascode LC-Neutralized Power Amplifier for 4:1-VSWR-Resilient Operations in Large-Scale Phased Arrays
ARGUS SPACE AG, Zurich, Switzerland 1 2 Large-scale mm-wave phased arrays are crucial for the success of next-generation 5G/6G communication. Yet, using a dense array of antennas inevitably leads to mutual coupling betwe
ISSCC 2025
Session 5
RF & Wireless
A Power-Efficient CORDIC-less Digital Polar Transmitter Using 1b DSM-Based PA Supporting 256-QAM
Dingxin Xu, Waleed Madany, Ashbir Aviat Fadila, Wenqian Wang, Yuang Xiong, Daxu Zhang, Garry Pranata Kusuma, Hiroyuki Sakai, Kazuaki Kunihiro, Atsushi Shirane, Kenichi Okada Institute of Science Tokyo, Tokyo, Japan CMOS
ISSCC 2025
Session 5
RF & Wireless
A 20W CMOS/LDMOS All-Digital Transmitter with Dynamic
Dieuwert Peter Nicolaas Mul1, Rob J Bootsman1, Mohammadreza Beikmirza1, Ossama El Boustani1, Yiyu Shen1, Daniel Maassen2, Bart van Velzen2, Mohadig Rousstia2, Ronald Koster2, John R Gajadharsing2, Thomas Fritzsch3, Morte
ISSCC 2025
Session 5
RF & Wireless
A 21-to-31GHz DPD-less Quadrature RFDAC with Invariant Impedance and Scalable LO Leakage
The increasing data-rates of modern wireless communication systems require transmitters with high linearity to support high-order QAM modulation and wide modulation bandwidths. Digital transmitters based on RF digital-to
ISSCC 2025
Session 6
Image Sensors
A 3-Stacked Hybrid-Shutter CMOS Image Sensor with Switchable 1.2µm-Pitch 50Mpixel Rolling Shutter and 2.4µm-Pitch 12.5Mpixel Global Shutter Modes for Mobile Applications
Yongjun Kim, Sanggwon Lee, Sungbong Park, Daehee Bae, Si Gyoung Koo, Masamichi Ito, Jae-hoon Jeon, Sol Yoon, Sung-Jae Byun, Sangyoon Kim, KwanSik Kim, Gihwan Cho, Joonho Lee, Tekyou Kim, Sungjae Jun, Jae-kyu Lee, Chang-R
ISSCC 2025
Session 6
Image Sensors
A 10.5mW Automotive Touch AFE IC Featuring Radiated EMI Reduction Based on Pipelined Dual-Frequency Modulation and Sine2 Waveform Shaping for CISPR 25 Class 5 Compliance
Samsung Electronics, Hwaseong, Korea 1 2 Recent automobiles increasingly incorporate touch-screen interfaces instead of traditional buttons and knobs. These automotive touch-screen sensors offer versatile functionality a
ISSCC 2025
Session 6
Image Sensors
An Asynchronous 160×90 Flash LiDAR Sensor with Dynamic Frame Rates of 5 to 250fps Based on Pixelwise ToF Validation via a Background-Light-Adaptive Threshold
Sogang University, Seoul, Korea 1 2 Over the past few decades, LiDAR technology has become a cornerstone in various fields, including autonomous vehicles, augmented reality, and robotics. Unlike traditional scanning LiDA
ISSCC 2025
Session 6
Image Sensors
SPAD Flash LiDAR with Chopped Analog Counter for 76m Range and 120klx Background Light
Korea 5 Samsung Electronics, Hwasung, Korea 1 2 Flash LiDAR sensors are becoming increasingly important in many automotive, space, and robotic applications. However, achieving long range, high depth resolution, and high
ISSCC 2025
Session 6
Image Sensors
A 400×400 3.24µm 117dB-Dynamic-Range 3-Layer Stacked Digital Pixel Sensor
Song Chen1, Zhao Wang4, Chiao Liu1, Yi-Hsuan Lin2, Sheng-Yeh Lai2, Hao-Ming Hsu2, Hirofumi Abe5, Kazuya Mori5, Hideyuki Fukuhara5, Chih-Hao Lin2, Toshiyuki Isozaki5, Wei-Chen Li2, Wei-Fan Chou2, Masayuki Uno5, Rimon Iken
ISSCC 2025
Session 6
Image Sensors
A 25.2Mpixel 120frames/s Full-Frame Global-Shutter CMOS Image Sensor with Pixel-Parallel ADC
(RS) currently dominate the market for consumer cameras, particularly interchangeable lens cameras (ILCs). Despite their widespread use, conventional sensors with RS, such as [1], have limitations in image expression due
ISSCC 2025
Session 6
Image Sensors
A 320×256 6.9mW 2.2mK-NETD 120.4dB-DR LW-IRFPA with Pixel-Paralleled Light-Driven 20b Current-to-Phase ADC
Technical Physics Chinese Academy of Sciences, Shanghai, China 1 2 Long-wavelength (LW) cryogenic (from 80 down to 40K) infrared focal plane arrays (IRFPAs) are extensively employed because of their sensitivity and rapid
ISSCC 2025
Session 6
Image Sensors
A 10b Source-Driver IC with All-Channel Automatic Offset Calibration and Slew-Rate-Enhanced Amplifier Achieving 2273μm2/Channel and 1.9mV DVO for 6285-PPI OLED-on-Silicon Displays
*Equally Credited Authors (ECAs) Recent microdisplays for augmented reality (AR) and virtual reality (VR) devices face distinct technical challenges compared to traditional displays, with the essential requirements being
ISSCC 2025
Session 6
Image Sensors
A Real-Time Pixel-Compensated Source-Driver IC with Dual-Slope Error Detection and Multi-Channel Time-Multiplexing Compensator for Compact OLED Displays
Active-matrix organic light-emitting diode (AMOLED) displays, especially those using lowtemperature polycrystalline silicon (LTPS) thin-film transistors (TFTs), have been widely used in mobile devices thanks to their hig
ISSCC 2025
Session 6
Image Sensors
A Compact 10b Source Driver IC with Delta-Sigma Pulse Width Modulation for Low-Voltage Digital Interpolation Achieving 1884µm2/Channel
flagship smartphones has contributed to better quality 3D image rendering and mobile gaming applications. However, high-resolution displays require source-driver ICs (SD-IC) with more channels, significantly increasing t
ISSCC 2025
Session 7
Wireline I/O
A 212.5Gb/s DSP-Based PAM-4 Transceiver with 50dB Loss Compensation for Large AI System Interconnects in 4nm FinFET
Ahmed ElShater2, Amr Khashaba2, Shih-Hao Huang1, Tsz-Bin Liu1, Atharav Atharav2, Joonyeong Lee2, Qaiser Nehal2, Mohamed Megahed2, Yusang Chun2, Cheng-En Shieh1, Vidhan Jolly2, SoonWon Kwon2, Hsin-Ta Chien1, Ke-Chung Wu1,
ISSCC 2025
Session 7
Wireline I/O
An 8-to-28GHz 8-Phase Clock Generator Using Dual-Feedback Ring Oscillator in 28nm CMOS
Multi-phase clock generation is among the most critical building blocks in high-speed wireline transceivers. The integrated jitter and phase error of the clocks often dictate the maximum available SNDR at higher frequenc
ISSCC 2025
Session 7
Wireline I/O
A 2.2pJ/b 212.5Gb/s PAM-4 Transceiver with >46dB Reach in 5nm FinFET
D. Prabakaran3, D. Storaska5, D. Zhou1, D. Visani1, E. Hsiao1, F. Chu1, F. Khan1, F. Lu1, G. Cui1, G. Wang1, J. Natonio5, J. Deng1, J. Ding1, J. Guo1, J. Gu1, J. Zang1, L. Jiang1, K.-M. Lu4, M. Hasan1, M. Kelly6, M. H. K
ISSCC 2025
Session 7
Wireline I/O
A 1.11pJ/b 224Gb/s XSR Receiver with Slice-Based CTLE and PI-Based Clock Generator in 12nm CMOS
Integrated Circuits, Beijing, China 1 2 Over the past few decades, process scaling and architecture advancements have led to an exponential increase in transceiver data rates. Recently, 224Gb/s DSP-based receivers (RXs)
ISSCC 2025
Session 7
Wireline I/O
A 112Gb/s DSP-Based PAM-4 Receiver with an LC-Resonator-Based CTLE for >52dB Loss Compensation in 4nm FinFET the CTLE_HF equivalent CM circuit in Fig. 7.4.3, the inductor coupling factor k can push the CM resonance frequency much higher than the cut-off frequency of the next stage’s SCC. Since the RLC network’s low-frequency impedance is small, which is given as a sum of the inductor ESR and a CM termination, the CTLE CM gain can be kept low over all frequency range.
GPUs, long-reach high-speed interconnects with data rates of 100Gb/s or higher are widely demanded for many different applications such as Ethernet/Optical standards or PCIe 7.0. Despite the latest advances in DSP-based
ISSCC 2025
Session 7
Wireline I/O
A 353mW 112Gb/s Discrete Multitone Wireline Receiver Datapath with Time-Based ADC in 5nm FinFET
demand for higher communication bandwidth between processors through wired interconnects in large-scale servers has been driving the need to increase the perlane data rate beyond the current 112Gb/s. Recently demonstrate
ISSCC 2025
Session 7
Wireline I/O
A 2.06pJ/b 106.25Gb/s PAM-4 Receiver with 3-Tap FFE and 1-Tap Speculative DFE in 28nm CMOS
The increasing demand for I/O bandwidth in data center pushes the data rate of serial links up to 100Gb/s. Although ADC-based receivers have powerful and flexible DSP equalization that can compensate for >20dB channel lo
ISSCC 2025
Session 7
Wireline I/O
A Reference-less CDR Using SAR-Based Frequency-Acquisition Technique Achieving 55ns Constant Band-Searching Time and up to 63.64Gb/s/µs Acquisition Speed
in applications that demand a continuous data rate due to their simplicity and cost-effectiveness, as they eliminate the need for an external reference [1-6]. The frequency acquisition (FA) speed of such CDRs is critical
ISSCC 2025
Session 7
Wireline I/O
A 60Gb/s NRZ Burst-Mode CDR with Cross-Injection Locking and Flash Phase Detector Achieving 0.13ns Reconfiguration Time in 28nm CMOS
bandwidth and thermal power bottlenecks [1]. The increasing demands of the AI-centric data center impose more stringent requirements on low latency and high bandwidth [2]. Rapidly reconfigurable photonic switch networks
ISSCC 2025
Session 8
Digital Circuits
Dynamic Guard-Band Features of the IBM zNext System
Sean M. Carey3, Alejandro Cook1, Karl Anderson3, Michael Romain3, Thomas Strach1, Pradeep Bhadravati Parashurama4, Aishwarya Tadkase4, Rahman Abber Tahir1, Luke Jenkins3, Kevin Low3, Eberhard Engler1 IBM Systems, Böbling
ISSCC 2025
Session 8
AI / ML
Run-Time Power Management System by On-Die Power Sensor with Silicon Machine Learning-Based Calibration in a 3nm Octa-Core CPU
Yuju Cho1, Rex Che-Yuan Liu1, Ericbill Wang1, You-Ming Tsao1, Hugh Mair2, Shih-Arn Hwang1 MediaTek, Hsinchu, Taiwan MediaTek, Austin, TX 1 2 For flagship smartphones, the gaming experience has become one of essential dem
ISSCC 2025
Session 8
Digital Circuits
A Dynamically Reconfigurable Digital-Integrated Voltage-Regulator Fabric for Energy-Efficient DVFS in Multi-Domain SoCs
Regulator (VR) architecture (Fig. 8.3.1), using Buck regulators to each drive a group of Low Dropout (LDO) regulated domains. The domain with the highest Vdd requirement within each group – the critical domain – sets the
ISSCC 2025
Session 8
Digital Circuits
A Command-Aware Hybrid LDO for Advanced HBM Interfaces with 150µA Quiescent Current and 20pF On-Chip Capacitor Achieving Sub-10mV Voltage Droop in 400ps Settling Time
KAIST, Daejeon, Korea 3 Kyung Hee University, Yongin, Korea 1 2 *Equally Credited Authors (ECAs) With the advent of the generative AI era, high-bandwidth memory (HBM) has emerged as an irreplaceable solution that can pro
ISSCC 2025
Session 8
Digital Circuits
A 0.024mm2 All-Digital Fractional Output Divider with 257fs Worst-Case Jitter Using Split-DTC-Based Background Calibration
Nanjing, China 1 2 In modern system-on-chips (SoCs), compact, low-jitter and low-power on-chip clock generators are essential for delivering multiple output frequencies to various modules, including microprocessors, IO i
ISSCC 2025
Session 8
Digital Circuits
A Dual VDD-Temperature Sensor Employing Sensor Fusion with 2.4°C, 9mV (±3σ) Inaccuracy in 65nm CMOS
escalated thermal and power delivery challenges in modern Systems-in-Package (SiPs) [1]. Increased power density and degraded thermal conductance intensify thermal hotspots. Meanwhile, workload-dependent supply-voltage (
ISSCC 2025
Session 8
Digital Circuits
Fine-Grained Spatial and Temporal Thermal Profiling of a 16nm CMOS Buck Converter and SoC Load-Current Emulator Using Low-Voltage Micron-Scale Thermal Sensors
Krishnan Ravichandran, James W. Tschanz, Vivek De Intel, Hillsboro, OR Localized hotspots across high-power-density monolithic systems-on-chip (SoCs) and heterogenous 3D SoCs with integrated voltage regulators (IVR) pose
ISSCC 2025
Session 8
Digital Circuits
An On-Cell Monitoring and Balancing System With Near-Field Communications for EV Batteries
Dukosi, Edinburgh, United Kingdom A battery cell monitoring system for automotive and grid energy storage applications is presented. As part of a battery management system (BMS) it enhances pack performance and reliabili
ISSCC 2025
Session 9
Power Management
An 85-to-230VAC to 3.3-to-4.6VDC 1.52W Capacitor-Drop Sigma-Floating-SC AC-DC Converter with 81.3% Peak Efficiency
Tsinghua University, Beijing, China 1 2 *Equally Credited Authors (ECAs) The internet-of-things (IoT) and smart home devices, such as smart power meters and smart remote control, have great demand for high-efficiency, lo
ISSCC 2025
Session 9
Power Management
A 93%-Peak-Efficiency Battery-Input 12-to-36V-Output Inductor-in-the-Middle Hybrid Boost Converter with Continuous Input and Output Currents and Fast Transient with No RHP Zero
University of Macau, Macau, China 3 Tsinghua University, Beijing, China 1 2 Recent emerging applications, such as LiDAR transceivers for autonomous driving and motor drivers for drones and robots, raise the requirements
ISSCC 2025
Session 9
Power Management
A 98.3%-Peak-Efficiency Single-Mode Hybrid Buck-Boost Converter with 7mV Maximum Output Ripple for Li-Ion Battery Management
Hefei CLT Microelectronics, Hefei, China 1 2 Hybrid buck-boost converters have been extensively studied for their ability to efficiently convert varying battery voltages (e.g., 2.8V to 4.2V) to a stable mid-3V output in
ISSCC 2025
Session 9
Power Management
A 400MHz Symbol-Power-Tracking (SPT) Supply Modulator with SPT-Adaptive-Biasing Network Supporting 5G FR2 CMOS PA
The 5G new-radio (NR) frequency-range-2 (FR2) for cellular communications supports a maximum channel bandwidth of 400MHz [1] and utilizes orthogonal frequency-division multiplexing (OFDM) to support high data rates with
ISSCC 2025
Session 9
Power Management
A 74W/48V Monolithic-GaN Integrated Adjustable Multilevel Supply Modulator for 5G Base-Station Massive-MIMO Arrays
Shenggang Dong2, Masoud Shahshahani2, Won Suk Choi2, Gary Xu2, Marcus Michel3, Ratul Das3,4, Robert Beach3, Hanh-Phuc Le1 University of California, San Diego, CA Samsung Research America, Plano, TX 3 Efficient Power Conv
ISSCC 2025
Session 9
Power Management
A 102ns/V 94.3%-Peak-Efficiency Symbol-Power-Tracking Supply Modulator for 5G NR Power Amplifiers
As 5G communication technology advances, the power consumption of radio frequency power amplifiers (RFPAs) in 5G systems has become increasingly critical. To enhance efficiency, Symbol Power Tracking (SPT) has emerged as
ISSCC 2025
Session 9
Power Management
A 6.78MHz Single-Stage Regulating Rectifier with Dual Outputs Simultaneously Charged in a Half Cycle Achieving 92.2% Efficiency and 131mW Output Power
IBM T. J. Watson Reseach Center, Yorktown Heights, NY 1 2 Wireless power transfer to implanted devices is an elegant solution that can obviate the need for batteries [1–5]. As more functions are implemented in the implan
ISSCC 2025
Session 9
Power Management
A 6.78MHz 94.2% Peak Efficiency Class-E Transmitter with Adaptive Real-Part Impedance Matching and Imaginary-Part Phase Compensation Achieving a 33W Wireless-Power-Transfer System
convenience. However, high efficiency is usually achieved at a specific load point in current wireless power transfer (WPT) systems rather than in a wide impedance range. The load varies greatly when charging state chang
ISSCC 2025
Session 9
Power Management
A 50W 98%-Efficiency High-Power Wireless-Charging System with an Acoustic Noise-Reduced ASK Modulation Technique and Internal Hybrid Voltage-/Current-Mode ASK Demodulation
mobile devices. The well-known and widely used Qi wireless power transfer (WPT) standard has been extended to version 2.0, now incorporating the magnetic power profile (MPP) standard in addition to the baseline power pro
ISSCC 2025
Session 9
Power Management
A Bi-Directional Dual-Path Boost-48V-Buck Hybrid Converter for High-Voltage Power-Transmission Cable in Light-Weight Humanoid Robots
UM Hetao IC Research Institute, Shenzhen, China 3 Tsinghua University, Beijing, China 1 *Equally Credited Authors (ECAs) Humanoid robots have high potential to replace human labors for various tasks in the near future [1
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