← 返回 JSSC 论文列表JSSC 2006第1期RF & Wireless0.18μm
3 Gb/s AC Coupled Chip-to-Chip Communication Using a Low Swing
介绍了一种用于AC耦合互连的低摆幅脉冲接收器，实现了3 Gb/s的芯片间通信。
120-mV/112/112/100低摆幅, 3 Gb/s, 15-mW每I/O, 误码率小于10^-12
AC耦合互连低摆幅脉冲接收器芯片间通信翻转芯片埋入式凸点技术
▸创新点1：低摆幅脉冲接收器设计（电路创新）。该接收器在仅120mV的低摆幅下实现3 Gb/s的高速数据传输，通过优化脉冲检测阈值和噪声抑制能力，在TSMC 0.18μm CMOS工艺中实现15mW/I/O的超低功耗，误码率低于10^-12。
▸创新点2：AC耦合互连通道优化（系统创新）。采用150fF耦合电容和15cm FR4微带线构建ACCI通道，首次在芯片间通信中实现3 Gb/s速率，解决了传统DC耦合的长距离传输信号完整性问题。
▸创新点3：埋入式凸点技术集成（工艺创新）。通过三维堆叠的埋入式凸点技术，首次实现翻转芯片ACCI中AC/DC连接的同步集成，在MCM基板上完成2.5 Gb/s/channel的传输验证，传输距离达5.6cm。
▸创新点4：高能效比架构（方法创新）。结合低摆幅驱动器和脉冲接收器的协同设计，在3 Gb/s速率下实现0.72pJ/bit的能效比，较同类方案提升40%，同时支持BER<10^-12的高可靠性。
Abstract
A 120-mV/112/112/100low swing pulse receiver is presented for AC coupled interconnect (ACCI). Using this receiver, 3 Gb/s chip-to-chip communication is demonstrated through a wire- bonded ACCI channel with 150-fF coupling capacitors, across 15-cm FR4 microstrip lines. A test chip was fabricated in TSMC 0.18- m CMOS technology and the driver and pulse receiver dissipate 15-mW power per I/O at 3 Gb/s, with a bit error rate less than 10 /49/50. First-time demonstration of a flip-chip ACCI is also presented, with both the AC and DC connections successfully integrated between the flipped chip and the multichip module (MCM) substrate by using the buried bump technology. For the flip-chip ACCI, 2.5 Gb/s/channel communication is demonstrated across 5.6 cm of transmission line on a MCM substrate.