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A 146-mm508-Gb Multi-Level NAND Flash Memory With 70-nm CMOS Technology Takahiko
采用70nm CMOS技术开发的多级NAND闪存，芯片面积减小4.9%，编程吞吐量达6MB/s。
146mm²芯片面积，6MB/s编程吞吐量，60MB/s读取吞吐量
多级NAND闪存CMOS技术芯片面积优化编程吞吐量读取吞吐量
▸创新点1：单边焊盘排列与紧凑核心架构（系统创新） - 通过优化芯片布局，将焊盘单边排列并采用紧凑核心架构，显著减少芯片面积至146 mm²，比传统设计缩小4.9%，提升了集成密度与成本效益。
▸创新点2：无块冗余替换的块地址扩展方案（方法创新） - 提出新型地址扩展技术，取消传统块冗余替换机制，简化存储管理流程，同时保持可靠性，进一步降低芯片面积与设计复杂度。
▸创新点3：多级单元编程与写入缓存结合（电路创新） - 通过MLC编程与写入缓存协同优化，实现6 MB/s的高编程吞吐量（4-KB页操作），性能接近二进制闪存，同时提升数据写入效率。
▸创新点4：邻近选择晶体管编程电压补偿技术（电路创新） - 采用动态电压补偿机制，减少编程过程中邻近晶体管的干扰，提升多级单元的数据精度与可靠性，支持高密度存储。
Abstract
An 8-Gb multi-level NAND Flash memory with
4-level programmed cells has been developed successfully. The
cost-effective small chip has been fabricated in 70-nm CMOS tech-
nology. To decrease the chip size, a one-sided pad arrangement
with compacted core architecture and a block address expansion
scheme without block redundancy replacement have been intro-
duced. With these methods, the chip size has been reduced to
146 mm
/50, which is 4.9% smaller than the conventional chip. In
terms of perform