A Reprogrammable EDGE Baseband and Multimedia Handset SoC With 6-Mbit Embedded DRAM Andrew M. Cofler, Francois Druilhe, Denis Dutoit, and

Abstract

A CMOS EDGE baseband and multimedia handset SoC features a dual core (microcontroller and DSP) architecture together with all the necessary interface logic and hardware ac- celerators interconnected by a multi-layer bus. The DSP memory hierarchy features an instruction cache coupled to a 6-Mbit em- bedded DRAM instruction memory allowing in the field software flexibility (for example dynamic upgrade of DSP software), while minimizing power and area (closely matching a ROM based solu- tion). The chip is implemented in a 130-nm 6-metal layer CMOS process and is packaged in a 12 12 ball-grid array. Full chip standby mode current is 690 A (with data retention), resulting in a 500 hour complete GSM/EDGE terminal autonomy.