A Sub-05-V Operating Embedded SRAM Featuring a Multi-Bit-Error-Immune Hidden-ECC

Abstract

The mobile multi-media applications require to lower the operating voltage of embedded SRAMs. The ECC circuit implementation for increasing soft-error and the access timing control that tracks access delay fluctuation in memory core should be considered for the low-voltage operation. A hidden error-check-and-correction (HECC) scheme compensated the access time penalty caused by the ECC logic on the output critical path. And a multi-column ECC word assignment (MCE) increased the multi-bit-error im