A Sub-0.5-V Operating Embedded SRAM Featuring a Multi-Bit-Error-Immune Hidden-ECC Scheme

Abstract

The mobile multi-media applications require to lower the operating voltage of embedded SRAMs. The ECC circuit implementation for increasing soft-error and the access timing control that tracks access delay fluctuation in memory core should be considered for the low-voltage operation. A hidden error-check-and-correction (HECC) scheme compensated the access time penalty caused by the ECC logic on the output critical path. And a multi-column ECC word assignment (MCE) increased the multi-bit-error immunity while using only 1-bit-correctable ECC which minimized area penalty. A source-level-adjusted direct sense amplifier (SLAD) and a write-replica circuit with an asymmetrical replica memory cell (WRAM) for the device-fluctu- ation-tolerant access control were also designed. A 130-nm CMOS 32-Kbit SRAM-macro was fabricated with these circuit tech- niques, which demonstrated: 1) 0.3-V operation with 6.8 MHz; 2) 30-MHz operation which is feasible for mobile use even at 0.4 V , while keeping 960 MHz at 1.5 V; and 3) a reduction by 3.6 /49/48/53 in soft-error rate compared with that of conventional ECC.