JSSC 2006第1期Clocking & PLLsDLL

Chip-Package Hybrid Clock Distribution Network and DLL for Low Jitter Clock Deli

提出一种芯片-封装混合时钟分配网络和DLL，实现极低抖动时钟传输。

500MHz下78ps峰峰值抖动（传统方案172ps），300mV电压降下80ps长期抖动（传统方案380ps）

时钟分配网络延迟锁定环低抖动芯片封装协同设计电源噪声抑制

▸采用无损封装层互连替代有损片上全局线

▸利用高频波导实现无中继时钟分配

▸抗电源噪声设计显著降低抖动

Abstract

This paper presents a chip-package hybrid clock distribution network and delay-locked loop (DLL) with which to achieve extremely low jitter clock delivery. The proposed hybrid clock distribution network and DLL provide digital noise-free and low-jitter clock signals by utilizing lossless package layer interconnections instead of lossy on-chip global wires with cas- caded repeaters. The lossless package layer interconnections become high-frequency waveguides and provide a repeater-free clock dist