Concordant Memory Design An Integrated Statistical Design Approach for Multi-Gig

Abstract

Concordant memory design incorporates fluctuation in device parameters statistically into signal-to-noise ratio anal- ysis in DRAM. In this design, the effective signal voltage of all cells in a chip is calculated, and the failed bit count of the chip is estimated. The proposed design approach gives us a quantitative evaluation of the memory array and assures 1.4-V array opera- tion of 100–nm–1-Gb DRAM. Calculated dependence of the failed bit count on the array voltage is in close agreement with