JSSC 2006第1期Power Management未明确提及Charge PumpDRAM

Design of a 128-Mb SOI DRAM Using the Floating Body Cell (FBC)

设计采用浮体单元（FBC）的128Mb SOI DRAM，通过优化感测放大器和参考电流生成技术提高数据稳定性和能效。

128Mb容量，SOI工艺

SOI DRAM浮体单元感测放大器电荷泵效应准非破坏性读取

▸采用浮体单元（FBC）技术实现数据存储

▸通过感测放大器（S/A）在每次读写周期中补充因电荷泵效应丢失的空穴，提高数据稳定性

▸采用多对平均虚拟单元生成精确参考电流，区分数据'1'和'0'

▸非对称操作感测放大器以降低功耗

▸利用准非破坏性读取特性实现DRAM的SRAM接口或隐藏刷新操作

Abstract

A 128-Mb SOI DRAM has been developed featuring the ﬂoating body cell (FBC). To keep the cell data state from being degraded by the word-line (WL) disturb due to the charge pumping and to reduce the refresh busy rate, a sense ampliﬁer (S/A) is arranged for every bit-line (BL) and replenishes data “1” cells’ bodies with holes which are lost by the disturb in every read and write cycle. The power is reduced by operating the S/As asymmetrically between the selected and the unselected thanks to that the number of holes to be replenished in the unselected S/As for charge pumping is two order of magnitude smaller than that required for writing the data “1”. The multi-pair averaging of dummy cells generates a very accurate reference current for distinguishing the data “1” and “0” and a Monte Carlo simulation shows that it achieves a sensing scheme robust enough to realize all good parts of the DRAM with a reasonable amount of redun- dancy. The cell’s feature of quasi-nondestructive read-out is also advantageous for making an SRAM interface of the DRAM or hiding refresh from uses without sacriﬁcing the access time.