Abstract
The write performance of the 1.8-V 64-Mb phase-
change random access memory (PRAM) has been improved, which
was developed based on 0.12-
m CMOS technology. For the im-
provement of RESET and SET distributions, a cell current reg-
ulator scheme and multiple step-down pulse generator were em-
ployed, respectively. The read access time and SET write time are
68 ns and 180 ns, respectively.