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PVT-Aware Leakage Reduction for On-Die Caches With Improved
提出一种自适应电路技术，显著减少SRAM泄漏，提升读取稳定性。
0.18-μm 1.8-V 16-kbyte SRAM testchip, 94.2% leakage reduction, <2% performance penalty, 25% improved static noise margin
SRAM泄漏自适应电路睡眠模式静态噪声容限工艺温度波动
▸创新点1：自适应电路技术，通过动态调整SRAM块的睡眠模式频率，优化泄漏电流减少效果，适应不同工艺和温度变化。
▸创新点2：运行时泄漏减少技术，结合架构访问行为，智能决定SRAM块进入睡眠模式的时机，显著降低泄漏功耗。
▸创新点3：自衰减电路生成周期性睡眠脉冲，根据泄漏条件自适应调整脉冲周期，在高泄漏条件下更频繁地进入睡眠模式。
▸创新点4：改进的SRAM静态噪声容限，通过优化存储单元设计，提升25%的静态噪声容限，增强读取稳定性。
Abstract
Effectiveness of previous SRAM leakage reduction techniques vary significantly as the leakage variation gets worse with process and temperature fluctuation. This paper proposes a simple circuit technique that adaptively trades off overhead energy for maximum leakage savings under severe leakage vari- ations. The proposed run-time leakage reduction technique for on-die SRAM caches considers architectural access behavior to determine how often the SRAM blocks should enter a sleep mode. A self-decay circuit generates a periodic sleep pulse with an adaptive pulse period, which puts the SRAM array into a sleep mode more frequently at high leakage conditions (fast process, high temperature) and vice versa . An 0.18- m 1.8-V 16-kbyte SRAM testchip shows 94.2% reduction in SRAM cell leakage at a performance penalty less than 2%. Measurement results also indicate that our proposed memory cell improves SRAM static noise margin by 25%.