← 返回 JSSC 论文列表JSSC 2006第2期RF & Wireless0.13μm CMOSVCOTransceiver
A 1.2-V RF Front-End With On-Chip VCO for PCS 1900 Direct Conversion Receiver in 0.13-/22m CMOS
本文介绍了一种用于PCS 1900直接转换接收器的1.2V RF前端设计,包含LNA、正交混频器和带增益控制的RC低通滤波器。
电压增益50 dB, 噪声系数3.9 dB, IIP3 9 dBm, IIP2 4330 dBm
RF前端直接转换接收器低噪声放大器正交混频器动态匹配
▸动态匹配技术抑制混频器开关的闪烁噪声
▸电流模式接口提升混频器线性度
▸低电压电路技术增强线性度和降低噪声
Abstract
In this paper, a 1.2-V RF front-end realized for the personal communications services (PCS) direct conversion receiver is presented. The RF front-end comprises a low-noise amplifier (LNA), quadrature mixers, and active RC low-pass filters with gain control. Quadrature local oscillator (LO) signals are generated on chip by a double-frequency voltage-controlled oscillator (VCO) and frequency divider. A current-mode interface between the downconversion mixer output and analog baseband input together with a dynamic matching technique simultaneously improves the mixer linearity, allows the reduction of flicker noise due to the mixer switches, and minimizes the noise contribution of the analog baseband. The dynamic matching technique is em- ployed to suppress the flicker noise of the common-mode feedback (CMFB) circuit utilized at the mixer output, which otherwise would dominate the low-frequency noise of the mixer. Various low-voltage circuit techniques are employed to enhance both the mixer second- and third-order linearity, and to lower the flicker noise. The RF front-end is fabricated in a 0.13- m CMOS process utilizing only standard process options. The RF front-end achieves a voltage gain of 50 dB, noise figure of 3.9 dB when integrated from 100 Hz to 135 kHz, IIP3 of 9 dBm, and at least IIP2 of/4330 dBm without calibration. The 4-GHz VCO meets the PCS 1900 phase noise specifications and has a phase noise of 132 dBc/Hz at 3-MHz offset.