← 返回 JSSC 论文列表JSSC 2006第2期RF & Wireless0.18-μmNeural Network Accelerator
A 600-MS/s 5-Bit Pipeline A/D Converter Using Digital
研究了一种用于串行链路接收器的600-MS/s 5位模数转换器，采用闭环流水线架构和数字参考校准技术。
600 MS/s, 5-bit, 70 mW, 0.18-μm CMOS
模数转换器流水线架构数字校准低功耗高速
▸创新点1：闭环流水线架构（系统创新） - 采用闭环设计的流水线架构显著提高了转换器的速度和精度，在600 MS/s的采样率下实现了25.6 dB的SNDR，同时保持低功耗（70 mW），适用于高速串行链路接收器。
▸创新点2：数字参考校准技术（方法创新） - 通过数字方式动态调整每个流水线级的参考电压，解决了传统校准技术的局限性，使SNDR在600 MS/s下提升了4.4 dB，同时DNL和INL分别优化至0.35 LSB和0.15 LSB。
▸创新点3：低输入电容设计（电路创新） - 输入电容仅为170 fF，降低了信号路径的负载，提高了系统的响应速度，并使其适合多路复用（interleaving）应用，增强了设计的灵活性和扩展性。
▸创新点4：高性能与低功耗平衡（系统创新） - 在0.18μm CMOS工艺下实现，兼顾了600 MS/s的高采样率和70 mW的低功耗，差分输入摆幅达400 mV，适用于1.8V供电环境，展现了优异的能效比。
Abstract
The design of a 600-MS/s 5-bit analog-to-digital (A/D) converter for serial-link receivers has been investigated. The A/D converter uses a closed-loop pipeline architecture. The input capacitance is only 170 fF, making it suitable for interleaving. To maintain low power consumption and increase the sampling rate beyond the amplifier settling limit, the paper proposes a calibration technique that digitally adjusts the reference voltage of each pipeline stage. Differential input swing is 400 mV /112-/112at 1.8-V supply. Measured performance includes 25.6 dB and 19 dB of SNDR for 0.3-GHz and 2.4-GHz input frequencies at 600 MS/s for the calibrated A/D converter. The suggested calibration method improves SNDR by 4.4 dB at 600 MS/s with 0.35 LSB of DNL and 0.15 LSB of INL. The 180 1500 m/50chip is fabricated in a 0.18- m standard CMOS technology and consumes 70 mW of power at 600 MS/s.