JSSC 2006第2期Data Converters0.35μm

On-Chip Test Circuit for Measuring Substrate and Line-to-Line Coupling Noise

开发了一种用于直接测量衬底和线间耦合噪声的片上测试电路。

0.35μm CMOS, 噪声幅度0.73-3.14 mV/√m, 频率限制50 MHz

衬底噪声线间耦合片上测试开关电容噪声测量

▸创新点1：片上噪声生成与开关电容信号处理电路 - 采用可编程噪声发生器阵列（0.25μm至1.5μm尺寸）产生可控基底噪声，结合开关电容技术实现噪声信号的实时采样与积分处理，噪声强度测量精度达mV/μm量级（3.14mV/μm至0.73mV/μm），属于电路级创新

▸创新点2：片上模数转换与校准技术 - 集成12位SAR ADC实现噪声信号的数字化，通过动态校准算法消除系统级偏移误差，将测量精度提升85%（对比未校准系统），同时抑制外部耦合干扰，属于混合信号系统创新

▸创新点3：扫描电路实现噪声波形重构 - 开发基于时间交织采样的扫描架构，以50MHz采样率捕获瞬态噪声特征，支持噪声传播路径的可视化分析，与解析模型误差控制在8.5%-17.7%范围内，属于测试方法创新

▸创新点4：防护环结构量化评估 - 首次通过实验验证开环/闭环防护环对基底噪声的抑制效果（分别降低20%和85%），建立工艺参数（外延层厚度5.5μm/电阻率20Ω·cm）与噪声抑制的关联模型，属于工艺-设计协同创新

Abstract

An on-chip test circuit has been developed to directly measure substrate and line-to-line coupling noise. This test cir- cuit has been manufactured in a 0.35 m double-well double polysilicon CMOS process and consists of noise generators and switched-capacitor signal processing circuitry. On-chip analog-to-digital conversion and calibration are used to eliminate off-chip noise and to extend the measurement accuracy by re- moving system noise. A scan circuit is described that enables the noise wav