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Patent Abstracts________________________________________________________________________ The Patent Abstracts and References cited are intended to provide the minimum information necessary for determining interest. The full text and images can be obtained from the U.S. Patent Office at http://www.uspto.gov. 6,914,492 July 5, 2005 Digital Programmable Delay Scheme With Automatic Calibration Inventors: Hui; Keven (Union City, CA) and Hao; Hong (Saratoga, CA).
数字可编程延迟方案，带自动校准功能，替代PLL和DLL。
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数字可编程延迟自动校准振荡器电路参考时钟可编程延迟单元
▸创新点1：替代传统PLL和DLL的延迟方案，提出了一种基于可编程延迟单元的数字延迟方法，通过自动校准技术实现更灵活的延迟控制，减少了电路复杂度和功耗。
▸创新点2：使用参考时钟校准振荡器时钟频率，通过双计数器设计（一个由参考时钟驱动，另一个由振荡器时钟驱动）实现高精度的频率校准，显著提升了时钟信号的稳定性和准确性。
▸创新点3：可编程延迟单元的动态调整机制，通过校准和控制逻辑实时监测和调整延迟参数，确保在不同工艺、电压和温度（PVT）条件下均能保持一致的延迟性能。
▸创新点4：整体电路设计紧凑且高效，结合了数字控制和模拟校准的优势，实现了小面积、低功耗和高性能的延迟解决方案，适用于多种集成电路应用场景。
Abstract
ed are intended to provide
the minimum information necessary for determining interest. The
full text and images can be obtained from the U.S. Patent Office at
http://www.uspto.gov.
6,914,492 July 5, 2005
Digital Programmable Delay Scheme With Automatic
Calibration
Inventors: Hui; Keven (Union City, CA) and Hao; Hong (Saratoga,
CA).
Assignee: LSI Logic Corporation (Milpitas, CA)
Filed: September 25, 2003.
/67/117/114/114/101/110/116 /85/58/83/58/67/108/97/115/115/58 /51/51/49/61/53/55/59/51 /50 /5