A 0.5-V 25-MHz 1-mW 256-Kb MTCMOS/SOI SRAM for Solar-Power-Operated Portable Personal Digital Equipment—Sure Write Operation by Using Step-Down Negatively Overdriven Bitline Scheme Nobutaro Shibata, Hiroshi Kiya, Shigehiro Kurita, Hidetaka Okamoto, Masa’aki Tan’no

Abstract

Multithreshold-voltage CMOS (MTCMOS) tech- nology has a great advantage in that it provides high-speed operation with low supply voltages of less than 1 V . A logic gate with low-V /116/104MOSFETs has a high operating speed, while a low-leakage power switch with a high-V /116/104MOSFET eliminates the off-leakage current during sleep time. By using MTCMOS circuits and silicon-on-insulator (SOI) devices, the authors have developed a 256-Kb SRAM for solar-power-operated digital equipment. A double-threshold-voltage MOSFET (DTMOS) is adopted for the power switch to further reduce the off leakage. As regards the SRAM core design, we consider a hybrid configuration consisting of high-V /116/104and low-V/116/104MOSFETs (that is, multi-V/116/104 CMOS). A new memory cell with a separate read-data path provides a larger readout current without degrading the static noise margin. A negatively overdriven bitline scheme guarantees sure write operation at ultralow supply voltages close to 0.5 V . In addition, a charge-transfer amplifier integrated with a selector and data latches for intrabus circuitry are installed to enhance the operating speed and/or reduce power dissipation. A 32K-word 8-bit SRAM chip, fabricated with the 0.35- m multi-V /116/104 CMOS/SOI process, has successfully operated at 25 MHz under typical conditions with 0.5-V (SRAM core) and 1-V (I/O buffers) power supplies. The power dissipation during sleep time is less than 0.4 W and that for 25-MHz operation is 1 mW, excludin