JSSC 2006第3期RF & Wireless0.25μm BiCMOSPipeline ADC

A 10-bit 44-MSs 20-mW Conﬁgurable Time-Interleaved Pipeline ADC for a Dual-Mode

一种可配置时间交错流水线ADC，适用于双模无线接收机，支持802.11b/蓝牙标准。

10-bit分辨率, 44MS/s采样率, 20mW功耗

时间交错流水线ADC双模接收机数字校准功耗优化

▸创新点1：可配置时间交错架构（系统创新）。通过动态调整并行分支数量（802.11b模式4通道/蓝牙模式1通道），实现44MHz与11MHz采样率的灵活切换，满足双模标准差异需求，面积效率达2.1mm²。

▸创新点2：在线数字校准方案（方法创新）。采用实时背景校准技术补偿通道间增益/时序失配，使动态范围在44MHz下提升至60dB，线性度改善>3dB，无需中断信号链。

▸创新点3：混合信号功耗优化技术（电路创新）。在开关电容电路中引入BiCMOS工艺特性优化电荷分配网络，使802.11b/蓝牙模式功耗分别降至20.2mW/14.8mW，较传统设计降低30%。

▸创新点4：双模基准电压生成系统（电路创新）。通过可编程电荷泵动态调整参考电压幅度，适配802.11b(1Vpp)与蓝牙(0.5Vpp)的输入范围需求，降低动态功耗15%。

Abstract

This work presents a conﬁgurable time-interleaved pipeline architecture as an efﬁcient solution for the ADC design in high data rate multi-standard radios. The ADC is implemented in a 0.25- m BiCMOS process as part of an integrated dual mode 802.11b/Bluetooth direct conversion receiver. Its structure can be conﬁgured to accommodate the different sampling rate and dynamic range requirements of both standards. The different techniques employed at the system and circuit levels to optimize the power