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A CMOS Mixed-Signal Clock and Data Recovery Circuit for OIF CEI-6G+
一款用于OIF CEI-6G背板收发器的低功耗CMOS混合信号时钟数据恢复电路
0.13μm CMOS, 1.2V, 6Gb/s, 24mW
时钟数据恢复混合信号低功耗背板收发器CMOS
▸创新点1：采用子采样架构实现低功耗（方法创新）。通过子采样技术，显著降低了时钟和数据恢复电路的功耗，使其在6 Gb/s的高速运行下仅消耗24 mW，适用于低功耗应用场景。
▸创新点2：数据模式无关的环路带宽设计（系统创新）。该设计确保了环路带宽不受数据模式影响，提高了系统的稳定性和适应性，适用于多种数据传输场景。
▸创新点3：相位插值器技术（电路创新）。通过相位插值器实现精确的相位控制，支持高达2000 ppm的频率跟踪范围，提升了时钟恢复的精度和灵活性。
▸创新点4：集成化设计（系统创新）。将相位检测器、环路滤波器、相位控制逻辑和相位插值器集成在0.13-μm CMOS工艺中，实现了高集成度和小面积（50 μm²），优化了系统性能。
Abstract
A CMOS low-power mixed-signal clock and data re- covery circuit is presented in this paper. It is designed for OIF CEI-6G+ LR backplane transceiver, and consists of a phase de- tector, loop filter, phase control logic, and phase interpolator. A unique subsampled architecture makes it possible for a low-power mixed-signal clock recovery loop running at a rate of 6 Gb/s. The proposed architecture has data pattern independent loop band- width. Fabricated in a 0.13- m CMOS technology in an area of /50/56/48 /49/48/48 m/50, the clock and data recovery loop exhibits a fre- quency tracking range up to 2000 ppm. The bit error rate is less than /49/48 /49/50with a pseudorandom bit sequence of length /50/51/49 /49. The power dissipation is 24 mW for clock and data recovery cir- cuits from a single 1.2-V supply.