A Three-Data Differential Signaling Over Four Conductors With Pre-Emphasis and Equalization: A CMOS Current

Abstract

A current-mode differential signaling of three data over two pairs of transmission lines increases the effective max- imum data rate per pair of transmission lines by about 37% over the conventional pure differential signaling. Each of two data is transmitted as a half-swing differential signal over a pair of trans- mission lines. The third data is transmitted as a half-swing com- plementary common-mode signal of the two pairs of transmission lines. Both a single-tap pre-emphasis and a single-tap decision feed- back equalizer are combined with this work. Adding a D flip-flop between the equalizer amplifier and the MUX embedded D flip-flop of receiver enables 4-Gb/s operation of receiver. The chip fabri- cated by using a 0.25- m CMOS process shows the maximum data rates of 4 and 3.2 Gb/s over 20- and 60-cm-long FR4 transmission lines, respectively, with bit-error rate below 1E-12.