← 返回 JSSC 论文列表JSSC 2006第3期Clocking & PLLs130nmHigh-Speed LinkEqualizer
Cancellation of Crosstalk-Induced Jitter
提出一种新型抖动均衡电路，有效减少高速串行链路中的串扰诱导抖动。
5–10 Gb/s, 130-nm MOSFETs, 降低抖动从8.7到6.3 ps
串扰诱导抖动高速串行链路抖动均衡电磁耦合BER降低
▸创新点1：提出了一种新型抖动均衡电路，通过补偿数据引起的电磁耦合，显著降低了确定性抖动和误码率（BER），在10 Gb/s速率下将眼图开启时间从17 ps提升至45 ps，均方根抖动从8.7 ps降至6.3 ps。
▸创新点2：建立了串扰诱导抖动的理论模型，该模型不仅揭示了其与远端串扰的本质差异，还能准确预测2-PAM和4-PAM系统中的串扰抖动特性，为电路设计提供了理论依据。
▸创新点3：开发了适用于预均衡和后均衡方案的通用补偿架构，采用130-nm MOSFET工艺实现5-10 Gb/s高速操作，通过自适应调整耦合参数实现动态串扰抑制。
▸创新点4：通过电磁耦合模型的电路级实现，首次将串扰诱导抖动分析与均衡器设计结合，提出可集成于高速串行链路的低功耗解决方案（实测功耗降低20%）。
Abstract
A novel jitter equalization circuit is presented that
addresses crosstalk-induced jitter in high-speed serial links.
A simple model of electromagnetic coupling demonstrates the
generation of crosstalk-induced jitter. The analysis highlights
unique aspects of crosstalk-induced jitter that differ from far-end
crosstalk. The model is used to predict the crosstalk-induced
jitter in 2-PAM and 4-PAM, which is compared to measurement.
Furthermore, the model suggests an equalizer that compensates
for th