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A 1-MHZ Bandwidth 3.6-GHz 0.18- /22m CMOS Fractional-N Synthesizer Utilizing a Hybrid PFD/DAC Structure for Reduced Broadband
提出一种高带宽低相位噪声的频率合成器架构，采用混合PFD/DAC电路实现分数N量化噪声主动消除。
1-MHz闭环带宽, 155 dBc/Hz相位噪声, 3.6-GHz输出
频率合成器相位噪声分数NPFD/DAC双频带
▸创新点1：混合相位/频率检测器和DAC电路（PFD/DAC）的创新设计，通过补偿失配和主动消除分数N量化噪声，实现了高闭环带宽和低输出相位噪声，具体表现为29 dB的量化噪声抑制和155 dBc/Hz的相位噪声性能。
▸创新点2：分数N量化噪声主动消除技术，无需校准即可显著降低量化噪声，提升系统整体性能，特别是在1-MHz闭环带宽下仍能保持优异的相位噪声特性。
▸创新点3：双频带直接调制发射器设计，支持900 MHz和1.8 GHz双频带操作，能够以271-kb/s的速率传输GMSK数据，且均方根相位误差小于3度，展现了出色的调制性能。
▸创新点4：片上频带选择分频器的集成，使得合成器能够灵活配置为双频带发射器，增强了系统的适用性和多功能性，同时保持了高性能指标。
Abstract
A frequency synthesizer architecture capable of simultaneously achieving high closed-loop bandwidth and low output phase noise is presented. The proposed topology uses a mismatch compensated, hybrid phase/frequency detector and digital-to-analog converter (PFD/DAC) circuit to perform active cancellation of fractional-N quantization noise. When compared to a classical second-order /6/1synthesizer, the prototype PFD/DAC synthesizer demonstrates 29 dB quantization noise suppression, without calibration, resulting in a fractional-N synthesizer with 1-MHz closed-loop bandwidth and 155 dBc/Hz phase noise at 20-MHz offset for a 3.6-GHz output. An on-chip band select divider allows the synthesizer to be configured as a dual-band (900 MHz/1.8 GHz) direct modulated transmitter capable of transmitting 271-kb/s GMSK data with less than 3 degrees of rms phase error.