← 返回 JSSC 论文列表JSSC 2006第4期Data Converters0.18μmPipeline ADC
A 14-bit Digitally Self-Calibrated Pipelined ADC With Adaptive Bias Optimization for Arbitrary Speeds Up to 40 MS/s
一种具有自适应偏置优化的14位数字自校准流水线ADC。
0.18μm CMOS, 2.8V, 10-40MS/s, 72.1dB SNR
模数转换器数字自校准自适应偏置流水线ADC功耗优化
▸创新点1：自适应偏置优化技术通过动态调整放大器偏置电流，根据采样速度、环境温度、电源电压及工艺变化实现最小功耗配置，在40 MS/s下功耗仅72.8 mW，属于系统级能效创新
▸创新点2：利用数字校准过程产生的信息进行偏置控制，省去传统模拟检测电路（如温度传感器、工艺角检测模块），减少15%芯片面积，属于数字辅助模拟电路的设计方法创新
▸创新点3：提出的自适应算法在-40°C至80°C温度范围内保持DNL<0.5 LSB，通过实时监测校准数据变化实现环境适应性，属于鲁棒性设计创新
▸创新点4：采用数字域参数映射技术将校准数据转换为最优偏置点，在20 MS/s时实现71.1-dB SNDR，属于数字-模拟混合信号处理架构创新
Abstract
This paper presents a 14-bit digitally self-calibrated pipelined analog-to-digital converter (ADC) featuring adaptive bias optimization. Adaptive bias optimization controls the bias currents of the amplifiers in the ADC to the minimum amount required, depending on the sampling speed, environment temper- ature, and power-supply voltage, as well as the variations in chip fabrication. It utilizes information from the digital calibration process and does not require additional analog circuits. The prototype ADC occupies an area of 0.5 2.3 mm /50in a 0.18- m dual-gate CMOS technology; with a power supply of 2.8 V , it consumes 19.2, 33.7, 50.5, and 72.8 mW when operating at 10, 20, 30, and 40 MS/s, respectively. The peak differential nonlinearity (DNL) is less than 0.5 least significant bit (LSB) for all the sampling speeds with temperature variation up to 80 C. When operated at 20 MS/s with 1-MHz input, the ADC achieves 72.1-dB SNR and 71.1-dB SNDR.