← 返回 JSSC 论文列表JSSC 2006第4期RF & Wireless90nm SOIPAM-4
A 22-Gb/s PAM-4 Receiver in 90-nm CMOS SOI Technology
90nm CMOS SOI工艺下22Gb/s PAM-4接收器设计
22Gb/s, BER<10^-12, 207mA@1.1V, 0.12mm²
PAM-4接收器CMOS SOI电流模式逻辑可编程终端模拟均衡器
▸创新点1：位切片架构数据路径 - 该方法创新通过将数据路径分解为多个并行处理的位切片单元，显著提高了数据处理速度和系统吞吐量，支持22 Gb/s的高速数据传输，同时降低了功耗和延迟。
▸创新点2：新型电压偏移放大器 - 该电路创新引入了一种可编程偏移的差分数据信号放大器，通过动态调整电压偏移，优化了信号完整性，有效降低了比特错误率（BER）至10^-12以下，适用于高频PAM-4信号处理。
▸创新点3：可编程匹配电阻CML偏置方案 - 该电路创新采用电流模式逻辑（CML）和可编程匹配电阻，显著减少了工艺变异对电路性能的影响，提高了系统的稳定性和一致性，同时支持灵活的偏置调整以适应不同工作条件。
▸创新点4：采样锁存器表征与集成方法 - 该方法创新提出了一种新颖的采样锁存器表征技术，并将其集成到数据路径中，通过精确校准和补偿，进一步提升了接收器的时序精度和信号恢复能力，适用于高精度高速通信系统。
Abstract
We report a receiver for four-level pulse-amplitude modulated (PAM-4) encoded data signals, which was measured to receive data at 22 Gb/s with a bit error rate (BER) 10 /49/50at a maximum frequency deviation of 350 ppm and a 2 /55 1 PRBS pattern. We propose a bit-sliced architecture for the data path, and a novel voltage shifting amplifier to introduce a programmable offset to the differential data signal. We present a novel method to characterize sampling latches and include them in the data path. A current-mode logic (CML) biasing scheme using programmable matched resistors limits the effect of process variations. The re- ceiver also features a programmable signal termination, an analog equalizer and offset compensation for each sampling latch. The measured current consumption is 207 mA from a 1.1-V supply, and the active chip area is 0.12 mm /50.