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A CMOS Finite Impulse Response Filter With a Crossover Traveling Wave Topology for Equalization up to 30 Gb/s
本文介绍了一种采用交叉行波拓扑的CMOS有限脉冲响应滤波器，具有高带宽和低功耗特性。
90nm CMOS, 1-V supply, 25-mW power, up to 30 Gb/s
有限脉冲响应滤波器行波拓扑CMOS差分螺旋线低功耗
▸改进的行波滤波器拓扑结构：通过修改传统行波滤波器拓扑，采用双跨导器叠加输出技术，实现了延迟-带宽-增益权衡的优化，使带宽在给定抽头间距和增益下翻倍，显著提升了高频性能（30 GHz以上）。
▸使用耦合差分螺旋线减小面积：创新性地采用耦合差分螺旋线作为延迟线，在保证信号完整性的同时将设计压缩至600μm×500μm的紧凑面积，解决了高频电路布局的空间挑战。
▸采用并行差分对实现低电压供电：通过用并行差分对替代传统的吉尔伯特单元放大器，实现了1V超低电压供电和仅25mW的功耗，为便携式高频设备提供了能效解决方案。
▸数字控制集成化：集成了抽头增益、前置放大器和调谐变容二极管的数字控制模块，提供了可编程性和适应性，支持高达30Gb/s的NRZ数据均衡，突破了现有CMOS均衡器速度限制。
Abstract
This paper describes a fully differential 3-tap finite impulse response filter in 90-nm CMOS. A traditional traveling wave filter topology is modified to alleviate its inherent delay–band- width–gain tradeoffs. Each tap gain is comprised of two transcon- ductors whose outputs superimpose with the same group delay, similar to a distributed amplifier. This doubles the bandwidth of the filter for a given tap spacing and gain. Digital control is pro- vided for the tap gains, an integrated pre-amplifier, and tuning var- actors. Coupled differential spirals are used in the delay lines to help the design fit into an area 600 m 500 m. A 1-V supply voltage and 25-mW power consumption are enabled by the use of parallel differential pairs for sign control of the transconductances instead of Gilbert cell amplifiers. The input return loss is better than 16 dB and the output return loss is better than 9 dB up to 30 GHz. Equalization of NRZ data over a coaxial cable channel was demonstrated up to 30 Gb/s, making it faster than any previously reported CMOS equalizer.