JSSC 2006第4期Data Converters0.35μmDACClock Generation

A Direct Digital Frequency Synthesizer With Fourth-Order Phase Domain /1/6Noise Shaper and 12-bit Current-Steering DAC

提出一种基于四阶相位域噪声整形的16位DDFS，采用0.35μm CMOS工艺，功耗200mW。

0.35μm CMOS, 3.3V, 300MS/s, SFDR>78dB, 200mW

直接数字频率合成器相位域噪声整形1/6插值器电流导向DACCMOS

▸创新点1：16位累加器（系统创新） - 采用高精度16位累加器实现相位累加，显著提升频率分辨率，支持更精细的频率调谐，同时保持低相位噪声，为DDFS系统提供稳定的相位生成基础。

▸创新点2：四阶相位域单级1/6插值器（方法创新） - 通过四阶噪声整形技术将有效相位位数减少4位，并利用1/6插值算法压缩ROM规模达16倍，在降低硬件开销的同时维持高动态范围（SFDR > 78 dB）。

▸创新点3：基于Q/50随机切换的12位电流导向DAC（电路创新） - 采用随机化切换策略抑制DAC的毛刺和谐波失真，在300 MS/s采样率下实现12位精度，显著提升输出频谱纯度。

▸创新点4：0.35-μm CMOS工艺集成（系统创新） - 将累加器、噪声整形器与DAC集成于1.11 mm²芯片面积，总功耗200 mW，实现高能效的小型化DDFS系统解决方案。

Abstract

This paper presents a direct digital frequency syn- thesizer (DDFS) with a 16-bit accumulator, a fourth-order phase domain single-stage /1/6 interpolator, and a 300-MS/s 12-bit current-steering DAC based on the Q /50Random Walk switching scheme. The /1/6 interpolator is used to reduce the phase trun- cation error and the ROM size. The implemented fourth-order single-stage /1/6 noise shaper reduces the effective phase bits by four and reduces the ROM size by 16 times. The DDFS prototype is fabricated in a 0.35- m CMOS technology with active area of 1.11 mm /50including a 12-bit DAC. The measured DDFS spu- rious-free dynamic range (SFDR) is greater than 78 dB using a reduced ROM with 8-bit phase, 12-bit amplitude resolution and a size of 0.09 mm /50. The total power consumption of the DDFS is 200 mW with a 3.3-V power supply.