← 返回 JSSC 论文列表JSSC 2006第4期Digital Circuits90nm SOI
A Fully Pipelined Single-Precision Floating-Point Unit in the Synergistic Proces
CELL处理器中的协同处理器单元(SPE)采用全流水线4路SIMD浮点单元，优化单精度乘加运算性能
5.6GHz@1.4V, 44.8GFlops, 768K晶体管/1.3mm²
浮点运算单元单精度SIMD流水线设计时钟门控
▸牺牲IEEE精确性换取高性能简化设计
▸采用细粒度时钟门控节能技术
▸架构/逻辑/电路协同设计实现目标
Abstract
The floating-point unit (FPU) in the synergistic
processor element (SPE) of a CELL processor is a fully pipelined
4-way single-instruction multiple-data (SIMD) unit designed to
accelerate media and data streaming with 128-bit operands. It
supports 32-bit single-precision floating-point and 16-bit integer
operands with two different latencies, six-cycle and seven-cycle,
with 11 FO4 delay per stage. The FPU optimizes the performance
of critical single-precision multiply–add operations. Since exact
r