A Low Leakage SRAM Macro With Replica Cell Biasing Scheme Yasuhisa Takeyama, Hiroyuki Otake, Osamu Hirabayashi, Keiichi Kushida, and

Abstract

For mobile applications of SRAMs, there is a need to reduce standby current leakages while keeping memory cell data. For this purpose, we propose a replica cell biasing scheme which controls the cell bias voltage by self-tuning using replica cells. This scheme minimizes the cell leakage regardless of the process fluctua- tions and the environmental conditions. In addition, leakage reduc- tion in row decoder circuits is also desirable, because standby cur- rent leakages in peripheral circuits are dominated by row decoders. We also propose a row decoder circuit which can reduce both the off-leakage and the gate-leakage in the row decoders. We fabri- cated a 90-nm 512-Kb low-leakage SRAM macro to verify the pro- posed leakage reduction techniques. With these techniques, 88% reduction of the standby leakage in the sleep mode and 40% re- duction of the leakage compared with the conventional diode clamp scheme are realized.