An Autonomous SRAM With On-Chip Sensors in an 80-nm Double Stacked Cell Technolo

Abstract

An active solution is proposed to overcome the uncer- tainty and fluctuation of the device parameters in nanotechnology SRAM. The proposed scheme is composed of sensing blocks, analysis blocks and control blocks. An on-chip timer, temperature sensor, substrate noise detector, and leakage current monitor are used to monitor internal status of chip during operation. From the sensed data, internal supply voltage, internal timing margin from decoding to sensing time, substrate noise from digital area