Abstract
This paper describes newly developed delay and power monitoring schemes for minimizing power consumption by means of the dynamic control of supply voltage /68/68and threshold voltage /84/72in active and standby modes. In the active mode, on the basis of delay monitoring results, either /68/68control or /84/72 control is selected to avoid any oscillation problem between them. In /68/68control, on the basis of delay monitoring results, /68/68is adjusted so as to be maintained at the minimum value at which the chip is able to operate for a given clock frequency. In /84/72 control, on the basis of power monitoring results, /84/72is adjusted so as to maintain a certain switching current /83/87/leakage current /76/69/65/75ratio known to indicate minimum power consumption. In the standby mode, the precision of power monitoring (which detects optimum body bias by comparing subthreshold current /83/85/66/84/72to substrate current /83/85/66) is improved by taking into consideration both the effects of lowering /68/68and the effects of the presence of gate-oxide leakage current. Experimental results with a 90-nm CMOS device indicate that use of the proposed power monitoring results in the successful minimizing of power consumption. It does so by making it possible to: 1) maintain the /83/87 /76/69/65/75ratio in the active mode and 2) detect optimum body bias conditions /40 /83/85/66/84/72/61 /83/85/66/41within an error of less than 20% with respect to actual minimum leakage current valu