← 返回 JSSC 论文列表JSSC 2006第5期Clocking & PLLs0.18μm CMOSDLL
A 072-GHz Self-Calibrated Multiphase Delay-Locked Loop
一种0.7-2GHz自校准多相延迟锁定环，采用数字校准电路减少时钟相位误差。
0.7-2GHz锁频范围，2GHz下峰峰值抖动18.9ps，均方根抖动2.5ps
延迟锁定环多相时钟自校准数字校准低抖动
▸数字校准电路自动校准多相时钟时序误差
▸启动控制电路扩展工作频率范围
▸校准完成后自动关闭校准电路以降低功耗和噪声
Abstract
A 0.7–2-GHz precise multiphase delay-locked
loop (DLL) using a digital calibration circuit is presented. In-
corporating with the proposed digital calibration circuit, the
mismatch-induced timing error among multiphase clocks in
the proposed DLL can be self-calibrated. When the calibration
procedure is finished, the digital calibration circuit can be turned
off automatically to save power dissipations and reduce noise
generations. A start controlled circuit is proposed to enlarge the
operating fr