← 返回 JSSC 论文列表JSSC 2006第5期Other0.18μm
A Simple On-Chip Repetitive Sampling Setup for the Quantification of Substrate No
提出一种片上重复采样技术，用于量化混合信号设计中的衬底噪声。
0.18μm CMOS, 200ps脉冲测量精度
衬底噪声混合信号设计等效时间采样差分锁存比较器波形重构
▸创新点1：等效时间衬底电压采样方法创新，通过重复采样技术扩展测量带宽，能够精确捕捉200 ps窄脉冲，显著提升噪声量化精度。
▸创新点2：电路创新，采用无显式输入采样保持的差分锁存比较器，简化电路结构，同时实现高带宽测量，降低系统复杂度。
▸创新点3：系统创新，提出有效重构脉冲波形特征的方法，无需复杂去卷积操作，显著提高噪声环境下波形重建的准确性。
▸创新点4：实验验证创新，在0.18-μm CMOS测试芯片上成功验证系统性能，展示了高带宽和精确波形捕捉能力，为混合信号设计提供可靠测试平台。
Abstract
The quantification of substrate noise is an important
issue in mixed-signal designs, where sensitive analog circuits are
embedded in a hostile digital environment. In this paper we present
an experimental environment to characterize the sensitivity of
embedded analog circuits to digitally generated substrate noise.
Our measurement technique is based on equivalent-time substrate
voltage sampling and uses a simple differential latch comparator
without explicit input sample-and-hold. A surprisingly