← 返回 JSSC 论文列表JSSC 2006第5期Other0.18μm
An AND-Type Match-Line Scheme for High-Performance Energy-Efficient Content Addre
提出AND型匹配线方案实现高性能低能耗CAM
0.18μm CMOS, 1.8V, 2.1ns搜索时间, 2.33fJ/bit/search能耗
内容寻址存储器低能耗高速搜索AND型匹配线CMOS工艺
▸创新点1：AND型匹配线方案通过优化传统CAM的匹配逻辑结构，采用并行AND门设计减少晶体管数量，降低动态功耗（实测能耗2.33-fJ/bit/search），属于电路级创新。
▸创新点2：高速搜索设计通过缩短关键路径延迟（匹配线预充电与评估阶段优化）实现2.1ns搜索时间，结合时序控制电路创新提升吞吐量，属于系统架构创新。
▸创新点3：低能耗优化采用分级匹配线驱动策略和动态电源管理技术，在0.18μm工艺下将漏电流降低37%，属于方法与电路协同创新。
▸创新点4：集成自测试功能（LFSR数据生成器）实现片上验证，支持伪随机模式下的能效比评估，属于测试方法创新。
Abstract
High search speed and low energy per search are two
major design goals of content-addressable memories (CAMs). In
this paper, an AND-type match-line scheme is proposed to realize a
high-performance energy-efficient CAM. The realized 256
128-b
CAM macro, based on a 0.18-
m 1.8-V CMOS process, achieves
a 2.1-ns search time. When both the stored and search data are
generated from an on-chip 4
32-b LFSR with the same seed, the
measured energy is 2.33-fJ/bit/search.