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Analysis of Reliability and Power Efficiency in Cascode Class-E PAs
分析级联E类功率放大器的可靠性与功率效率，提出优化设计方法。
0.13-µm CMOS, 67% PAE, 23 dBm peak power, 1.4–2 GHz bandwidth
级联E类功率放大器功率效率可靠性CMOS耗散机制
▸识别级联实现特有的新耗散机制
▸提出减少该耗散机制的电路解决方案
▸在1.7GHz下实现67%的功率附加效率
Abstract
Power efficiency in switched common source class-E amplifiers is usually obtained at the expense of device stress. Device stacking is a viable way to reduce voltage drops across a single de- vice, improving long-term reliability. In this paper, we focus on cas- code-based topologies, analyzing the loss mechanisms and giving direction to optimize the design. In particular, a new dissipative mechanism, peculiar of the cascode implementation, is identified and a circuit solution to minimize its effect is proposed. Prototypes, realized in a 0.13- m CMOS technology demonstrate 67% PAE while delivering 23 dBm peak power at 1.7 GHz. Good bandwidth was also realized with greater than 60% PAE over the frequency range of 1.4–2 GHz.