Constant-Ratio-Coupled Multi-Grain Digital Synchronizer With Flexible Input-Output Delay Selection for Versatility in Low-Power Applications

Abstract

The constant-ratio-coupled multi-grain digital syn- chronizer (CRC-MG synchronizer) is proposed as a means for making high-speed connections with very low power consumption, both among multiple chips such as processors, controllers, and storage devices, and among on-chip modules. The synchronizer not only provides a wide range of operating frequencies, but is fast locking and only occupies a small area on chip. Therefore, it contributes to large reductions in power consumption and costs. It is suitable for use in various low-power systems (e.g., bat- tery-hungry mobile appliances and low-cost consumer electronic products). Three major techniques were applied to the design: 1) a multi-grain structure for the delay elements, which greatly reduces the number of gates while facilitating locking in a very small number of clock cycles; 2) constant-ratio-coupled (CRC) delay lines (measurement versus generation) for flexible selection of the input-output delay; and 3) a new lock stage decision circuit (LSDC) scheme, conferring excellent testability. Moreover, the architecture is all-digital, and thus it has high process portability. By applying these techniques to a DDR memory interface circuit for a mobile application processor fabricated in 130-nm tech- nology, we were able to reduce power consumption by 42% and chip area by 65% compared with a conventional implementation. Furthermore, the novel design spans a frequency range covering 12 times the minimum frequency.