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High-Speed Circuit Designs for Transmitters in Broadband Data Links
本文提出了多种高速电路设计技术，用于宽带数据链路的发射器。
20 Gb/s, 22 mW, 1.8-V, 90 dBc/Hz, 0.2 ps rms, 4.5 ps pp
高速电路宽带数据链路发射器相位噪声时钟乘法
▸创新点1：内部峰值技术 - 通过结合多种峰值技术和门控开关，显著提升了多路复用器的操作速度至20 Gb/s，同时仅消耗22 mW功率，实现了高效能的高速数据传输。
▸创新点2：差分堆叠电感 - 在压控振荡器中采用差分堆叠电感设计，实现了在1 MHz偏移下90 dBc/Hz的相位噪声，且最低功耗仅为1 mW，优化了振荡器的性能与功耗平衡。
▸创新点3：双环PLL架构 - 结合三阶环路滤波器的双环PLL架构，使时钟乘法单元输出抖动低至0.2 ps rms，峰值抖动为4.5 ps pp，同时功耗仅为40 mW，提升了时钟信号的稳定性和精度。
▸创新点4：门控开关技术 - 在多路复用器中引入门控开关技术，进一步优化了电路的动态功耗管理，提高了整体系统的能效比。
Abstract
Various high-speed techniques including internal
peaking, differentially stacked inductor, and dual-loop PLL for
wireline communications are proposed, analyzed, and verified
by means of three independent circuits. A multiplexer incorpo-
rates multiple peaking techniques and gate control switching to
achieve an operation speed of 20 Gb/s while consuming 22 mW
from a 1.8-V supply. A voltage-controlled oscillator employing
differentially stacked inductor accomplishes a phase noise of
90 dBc/Hz at 1-