Highly Linear 0.18-/22m CMOS Power Amplifier With Deep n-Well Structure

Abstract

The linearity of a 0.18- m CMOS power amplifier (PA) is improved by adopting a deep n-well (DNW). To find the reason for the improvement, bias dependent nonlinear parame- ters of the test devices are extracted from a small-signal model and a Volterra series analysis for an optimized nMOS PA with a proper matching circuit is carried out. From the analysis, it is re- vealed that the DNW of the nMOS lowers the harmonic distor- tion generated from the intrinsic gate-source capacitance /40 /41, which is the dominant nonlinear source, and partially from drain junction capacitance /40 /41. Single-ended and differential PAs for 2.45-GHz WLAN are designed and fabricated using a 0.18- m standard CMOS process. The single-ended PA with the DNW im- proves IMD3 and IMD5 about 5 dB with identical power perfor- mances, i.e., 20 dBm of /111/117/116, 18.7 dB of power gain and 31% of power-added efficiency (PAE) at /49/100/66. The IMD3 and IMD5 are below 40 dBc and 47 dBc, respectively. The differential PA with the DNW also shows about 7 dB improvements of IMD3 and IMD5 with 20.2 dBm of /111/117/116, 18.9 dB of power gain and 35% of PAE at /49/100/66. The IMD3 and IMD5 are below 45 dB and 57 dBc, respectively. These performances of the linear PAs are state-of-the-art results.