← 返回 JSSC 论文列表JSSC 2006第6期Clocking & PLLs0.18μmCDR
A 155.52 Mbps–3.125 Gbps Continuous-Rate Clock and Data
一款支持155.52 Mbps至3.125 Gbps连续速率时钟数据恢复电路，采用全速率Bang-Bang相位检测器。
0.18μm CMOS, 95mW@3.125Gbps, BER<10^-12
时钟数据恢复连续速率Bang-Bang相位检测器频率检测器正交分频器
▸全速率Bang-Bang相位检测器
▸消除谐波锁定问题的频率检测器
▸生成精确正交相位的正交分频器
Abstract
A 155.52 Mbps–3.125 Gbps continuous-rate clock and data recovery (CDR) circuit using the full-rate bang-bang phase detector is presented. A frequency detector is proposed to eliminate the harmonic locking problem even with a wide range of data rates and its theoretical analysis is also discussed. A quadrature divider is also presented to generate the clocks with accurate quadrature phases. This CDR circuit has been realized in a 0.18- m CMOS process and its die area is /49 /49 /48 /56mm/50. It consumes 95 mW at the highest bit rate of 3.125 Gbps. It can recover the NRZ data of a /50/51/49 /49PRBS with the bit rate ranging from 155.52 Mbps to 3.125 Gbps for the incremental frequency acquisition and the NRZ data of a /50/55 /49PRBS for the decremental frequency acquisition. All the measured bit error rates are less than /49/48 /49/50.