← 返回 JSSC 论文列表JSSC 2006第6期Digital Circuits0.35-μmNeural Network Accelerator
A 75-dB Image Rejection IF-Input Quadrature-Sampling SC 61Modulator
一种通过时间共享关键电路组件解决I/Q失配问题的IF输入正交采样SC调制器。
0.35-μm CMOS, 0.57 mm², 200-kHz信号带宽, 75 dB图像抑制比
正交采样I/Q失配开关电容数字模拟转换器图像抑制比
▸时间共享I/Q通道的关键电路组件
▸对I/Q相位不平衡不敏感的时钟方案
▸第三阶单环1位低通调制器设计
Abstract
Quadrature sampling of intermediate frequency (IF)
signals is subject to the well-known problem of gain and phase mis-
matches between the in-phase (I) and quadrature (Q) channels.
This paper presents an IF-input quadrature-sampling switched-
capacitor (SC)
/6/1modulator that circumvents the I/Q mismatch
problem by time-sharing between the I and Q channels the critical
circuit components, namely, the sampling capacitor and the capac-
itor of the first-stage feedback digital-to-analog converter (D